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isp1161a1 universal serial bus single-chip host and device controller rev. 03 23 december 2004 product data 1. general description the isp1161a1 is a single-chip universal serial bus (usb) host controller (hc) and device controller (dc). the host controller portion of the isp1161a1 complies with universal serial bus speci?cation rev. 2.0, supporting data transfer at full-speed (12 mbit/s) and low-speed (1.5 mbit/s). the device controller portion of the isp1161a1 also complies with universal serial bus speci?cation rev. 2.0, supporting data transfer at full-speed (12 mbit/s). these two usb controllers, the hc and the dc, share the same microprocessor bus interface. they have the same data bus, but different i/o locations. they also have separate interrupt request output pins, separate dma channels that include separate dma request output pins and dma acknowledge input pins. this makes it possible for a microprocessor to control both the usb hc and the usb dc at the same time. the isp1161a1 provides two downstream ports for the usb hc and one upstream port for the usb dc. each downstream port has an overcurrent (oc) detection input pin and power supply switching control output pin. the upstream port has a v bus detection input pin.the isp1161a1 also provides separate wake-up input pins and suspended status output pins for the usb hc and the usb dc, respectively. this makes power management ?exible. the downstream ports for the hc can be connected with any usb compliant devices and hubs that have usb upstream ports. the upstream port for the dc can be connected to any usb compliant usb host and usb hubs that have usb downstream ports. the hc is adapted from the open host controller interface speci?cation for usb release 1.0a , referred to as ohci in the rest of this document. the dc is compliant with most usb device class speci?cations such as imaging class, mass storage devices, communication devices, printing devices and human interface devices. the isp1161a1 is well suited for embedded systems and portable devices that require a usb host only, a usb device only, or a combination of a con?gurable usb host and usb device. the isp1161a1 brings high ?exibility to the systems that have it built-in. for example, a system that uses an isp1161a1 allows it not only to be connected to a pc or usb hub with a usb downstream port, but also to be connected to a device that has a usb upstream port such as a usb printer, usb camera, usb keyboard or a usb mouse. therefore, the isp1161a1 enables point-to-point connectivity between embedded systems. an interesting application example is to connect an isp1161a1 hc with an isp1161a1 dc. consider an example of an isp1161a1 being used in a digital still camera (dsc) design. figure 1 shows an isp1161a1 being used as a usb dc. figure 2 shows an isp1161a1 being used as a usb hc. figure 3 shows an isp1161a1 being used as a usb hc and a usb dc at the same time.
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 2 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 1. isp1161a1 operating as a usb device. fig 2. isp1161a1 operating as a stand-alone usb host. fig 3. isp1161a1 operating as both usb host and device simultaneously. 004aaa173 m p system memory m p isp1161a1 host/ device m p bus i/f usb i/f usb device usb cable usb i/f embedded system pc (host) dsc 004aaa174 m p system memory m p isp1161a1 host/ device m p bus i/f usb host usb cable usb i/f embedded system usb i/f printer (device) dsc 004aaa175 m p system memory m p isp1161a1 host/ device m p bus i/f usb i/f usb device usb cable usb cable usb host usb i/f usb i/f embedded system pc (host) usb i/f printer (device) dsc
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 3 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 2. features n complies with universal serial bus speci?cation rev. 2.0 n the host controller portion of the isp1161a1 supports data transfer at full-speed (12 mbit/s) and low-speed (1.5 mbit/s) n the device controller portion of the isp1161a1 supports data transfer at full-speed (12 mbit/s) n combines the hc and the dc in a single chip n on-chip dc complies with most usb device class speci?cations n both the hc and the dc can be accessed by an external microprocessor via separate i/o port addresses n selectable one or two downstream ports for the hc and one upstream port for the dc n high-speed parallel interface to most of the generic microprocessors and reduced instruction set computer (risc) processors such as: u hitachi ? superh? sh-3 and sh-4 u mips-based? risc u arm7?, arm9?, strongarm ? n maximum 15 mbyte/s data transfer rate between the microprocessor and the hc, 11.1 mbyte/s data transfer rate between the microprocessor and the dc n supports single-cycle and burst mode dma operations n up to 14 programmable usb endpoints with 2 ?xed control in/out endpoints for the dc n built-in separate fifo buffer ram for the hc (4 kbytes) and dc (2462 bytes) n endpoints with double buffering to increase throughput and ease real-time data transfer for both dc transfers and hc isochronous (iso) transactions n 6 mhz crystal oscillator with integrated pll for low emi n controllable lazyclock (100 khz 50 %) output during suspend n clock output with programmable frequency (3 mhz to 48 mhz) n software controlled connection to usb bus (softconnect) on upstream port for the dc n good usb connection indicator that blinks with traf?c (goodlink) for the dc n software selectable internal 15 k w pull-down resistors for hc downstream ports n dedicated pins for suspend sensing output and wake-up control input for ?exible applications n global hardware reset input pin and separate internal software reset circuits for hc and dc n operation from a 5 v or a 3.3 v power supply n operating temperature range - 40 cto + 85 c n available in two lqfp64 packages (sot314-2 and sot414-1).
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 4 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 3. applications n personal digital assistant (pda) n digital camera n third-generation (3-g) phone n set-top box (stb) n information appliance (ia) n photo printer n mp3 jukebox n game console. 4. ordering information table 1: ordering information type number package name description version isp1161a1bd lqfp64 plastic low pro?le quad ?at package; 64 leads; body 10 10 1.4 mm sot314-2 isp1161a1bm lqfp64 plastic low pro?le quad ?at package; 64 leads; body 7 7 1.4 mm sot414-1
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x philips semiconductors isp1161a1 usb single-chip host and device controller 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 03 23 december 2004 5 of 136 5. block diagram fig 4. block diagram. 004aaa176 16 15 k w gnd host/ device automux host bus interface device bus interface clock recovery power switching overcurrent detection usb transceiver usb transceiver pll clock recovery goodlink programmable divider host controller device controller ping ram pong ram voltage regulator internal supply internal reset 3.3 v v cc power-on reset v reg(3.3) v hold1 dgnd gl clkout 7 1, 8, 15, 18, 35, 45, 62 2 usb transceiver itl0 (ping ram) itl1 (pong ram) isp1161a1 h_wakeup to/ from microprocessor h_psw1 46 43 41 38 19 v hold2 24 58 57 2 to 7, 9 to 14, 16, 17, 63, 64 40 42 33 22 21 23 60 59 28 27 34 26 25 30 29 37 36 32 56 n.c. 61, 20 44 47 54 55 50 51 52 53 39 48 49 xtal1 xtal2 h_psw2 h_oc1 h_oc2 d_vbus device controller host controller usb bus upstream port usb bus downstream ports h_dm1 h_dp1 h_dm2 h_dp2 d_dm d_dp h_suspend ndp_sel d0 to d15 rd dack2 dack1 eot dreq1 dreq2 int2 int1 d_wakeup d_suspend reset alt ram 6 mhz host bus device bus 4 1.5 k w 3.3 v softconnect agnd cs wr a1 a0
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 6 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 5. host controller sub-block diagram. mgt930 register access dma handler power-on reset itl0 ram atl ram itl1 ram m p handler pdt_list process usb transceiver usb bus h_dp1 h_dm1 h_dp2 h_dm2 philips sie clock recovery m p interface usb interface philips shc core memory block host controller sub-blocks bus i/f host bus i/f frame manage- ment usb state memory management unit fig 6. device controller sub-block diagram. mgt931 m p handler dma handler power-on reset ep handler philips sie d_dp usb bus d_dm usb transceiver memory management unit integrated ram bus i/f clock recovery 3.3 v goodlink gl softconnect device bus i/f device controller sub-blocks
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 7 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 6. pinning information 6.1 pinning 6.2 pin description fig 7. pin con?guration lqfp64. isp1161a1bd isp1161a1bm 004aaa177 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 d_dm h_psw2 h_psw1 dgnd 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 d1 d0 dgnd n.c. a1 a0 v reg(3.3) agnd v cc h_oc2 h_oc1 h_dp2 h_dm2 h_dp1 h_dm1 d_dp 49 dgnd d2 d3 d4 d5 d6 dgnd d8 d10 d11 d7 d9 d13 dgnd d14 d15 dgnd v hold1 n.c. rd wr v hold2 d12 cs test int2 int1 dack2 dack1 dreq2 dreq1 reset d_suspend dgnd eot ndp_sel xtal2 xtal1 h_suspend h_wakeup d_vbus gl d_wakeup clkout table 2: pin description for lqfp64 symbol [1] pin type description dgnd 1 - digital ground d2 2 i/o bit 2 of bidirectional data; slew-rate controlled; ttl input; three-state output d3 3 i/o bit 3 of bidirectional data; slew-rate controlled; ttl input; three-state output d4 4 i/o bit 4 of bidirectional data; slew-rate controlled; ttl input; three-state output d5 5 i/o bit 5 of bidirectional data; slew-rate controlled; ttl input; three-state output
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 8 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. d6 6 i/o bit 6 of bidirectional data; slew-rate controlled; ttl input; three-state output d7 7 i/o bit 7 of bidirectional data; slew-rate controlled; ttl input; three-state output dgnd 8 - digital ground d8 9 i/o bit 8 of bidirectional data; slew-rate controlled; ttl input; three-state output d9 10 i/o bit 9 of bidirectional data; slew-rate controlled; ttl input; three-state output d10 11 i/o bit 10 of bidirectional data; slew-rate controlled; ttl input; three-state output d11 12 i/o bit 11 of bidirectional data; slew-rate controlled; ttl input; three-state output d12 13 i/o bit 12 of bidirectional data; slew-rate controlled; ttl input; three-state output d13 14 i/o bit 13 of bidirectional data; slew-rate controlled; ttl input; three-state output dgnd 15 - digital ground d14 16 i/o bit 14 of bidirectional data; slew-rate controlled; ttl input; three-state output d15 17 i/o bit 15 of bidirectional data; slew-rate controlled; ttl input; three-state output dgnd 18 - digital ground v hold1 19 - voltage holding pin; internally connected to the v reg(3.3) and v hold2 pins. when v cc is connected to 5 v, this pin will output 3.3 v, hence do not connect it to 5 v. when v cc is connected to 3.3 v, this pin can either be connected to 3.3 v or left unconnected. in all cases, decouple this pin to dgnd. n.c. 20 - no connection cs 21 i chip select input rd 22 i read strobe input wr 23 i write strobe input v hold2 24 - voltage holding pin; internally connected to the v reg(3.3) and v hold1 pins. when v cc is connected to 5 v, this pin will output 3.3 v, hence do not connect it to 5 v. when v cc is connected to 3.3 v, this pin can either be connected to 3.3 v or left unconnected. in all cases, decouple this pin to dgnd. dreq1 25 o hc dma request output (programmable polarity); signals to the dma controller that the isp1161a1 wants to start a dma transfer; see section 10.4.1 dreq2 26 o dc dma request output (programmable polarity); signals to the dma controller that the isp1161a1 wants to start a dma transfer; see section 13.1.4 d a ck1 27 i hc dma acknowledge input; when not in use, this pin must be connected to v cc via an external 10 k w resistor table 2: pin description for lqfp64 continued symbol [1] pin type description
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 9 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. d a ck2 28 i dc dma acknowledge input; when not in use, this pin must be connected to v cc via an external 10 k w resistor int1 29 o hc interrupt output; programmable level, edge triggered and polarity; see section 10.4.1 int2 30 o dc interrupt output; programmable level, edge triggered and polarity; see section 13.1.4 test 31 o test output; used for test purposes only; this pin is not connected during normal operation reset 32 i reset input (schmitt trigger); a low level produces an asynchronous reset (internal pull-up resistor) ndp_sel 33 i indicates to the hc software the number of downstream ports (ndp) present: 0 select 1 downstream port 1 select 2 downstream ports only changes the value of the ndp ?eld in the hcrhdescriptora register; both ports will always be enabled; see section 10.3.1 (internal pull-up resistor) eot 34 i dma master device to inform the isp1161a1 of end of dma transfer; active level is programmable; see section 10.4.1 dgnd 35 - digital ground d_suspend 36 o dc suspend state indicator output; active high d_wakeup 37 i dc wake-up input; generates a remote wake-up from suspend state (active high); when not in use, this pin must be connected to dgnd via an external 10 k w resistor (internal pull-down resistor) gl 38 o goodlink led indicator output (open-drain, 8 ma); the led is default on, blinks off upon usb traf?c; to connect a led use a series resistor of 470 w (v cc = 5.0 v) or 330 w (v cc = 3.3 v) d_vbus 39 i dc usb upstream port v bus sensing input; when not in use, this pin must be connected to dgnd via a 1 m w resistor h_wakeup 40 i hc wake-up input; generates a remote wake-up from suspend state (active high); when not in use, this pin must be connected to dgnd via an external 10 k w resistor (internal pull-down resistor) clkout 41 o programmable clock output (3 mhz to 48 mhz); default 12 mhz h_suspend 42 o hc suspend state indicator output; active high xtal1 43 i crystal input; connected directly to a 6 mhz crystal; when xtal1 is connected to an external clock source, pin xtal2 must be left open xtal2 44 o crystal output; connected directly to a 6 mhz crystal; when pin xtal1 is connected to an external clock source, this pin must be left open table 2: pin description for lqfp64 continued symbol [1] pin type description
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 10 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] symbol names with an overscore (e.g. name) represent active low signals. dgnd 45 - digital ground h_psw1 46 o power switching control output for downstream port 1; open-drain output h_psw2 47 o power switching control output for downstream port 2; open-drain output d_dm 48 ai/o usb d - data line for dc upstream port; when not in use, this pin must be left open d_dp 49 ai/o usb d+ data line for dc upstream port; when not in use, this pin must be left open h_dm1 50 ai/o usb d - data line for hc downstream port 1 h_dp1 51 ai/o usb d+ data line for hc downstream port 1 h_dm2 52 ai/o usb d - data line for hc downstream port 2; when not in use, this pin must be left open h_dp2 53 ai/o usb d+ data line for hc downstream port 2; when not in use, this pin must be left open h_oc1 54 i overcurrent sensing input for hc downstream port 1 h_oc2 55 i overcurrent sensing input for hc downstream port 2 v cc 56 - power supply voltage input (3.0 v to 3.6 v or 4.75 v to 5.25 v). this pin supplies the internal 3.3 v regulator input. when connected to 5 v, the internal regulator will output 3.3 v to pins v reg(3.3) ,v hold1 and v hold2 . when connected to 3.3 v, it will bypass the internal regulator. agnd 57 - analog ground v reg(3.3) 58 - internal 3.3 v regulator output; when pin v cc is connected to 5 v, this pin outputs 3.3 v. when pin v cc is connected to 3.3 v, connect this pin to 3.3 v. a0 59 i address input; selects command (a0 = 1) or data (a0 = 0) a1 60 i address input; selects automux switching to dc (a1 = 1) or automux switching to hc (a1 = 0); see ta b l e 3 n.c. 61 - no connection dgnd 62 - digital ground d0 63 i/o bit 0 of bidirectional data; slew-rate controlled; ttl input; three-state output d1 64 i/o bit 1 of bidirectional data; slew-rate controlled; ttl input; three-state output table 2: pin description for lqfp64 continued symbol [1] pin type description
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 11 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7. functional description 7.1 pll clock multiplier a 6 mhz to 48 mhz clock multiplier phase-locked loop (pll) is integrated on-chip. this allows for the use of a low-cost 6 mhz crystal, which also minimizes emi. no external components are required for the operation of the pll. 7.2 bit clock recovery the bit clock recovery circuit recovers the clock from the incoming usb data stream using a 4 times over-sampling principle. it is able to track jitter and frequency drift as speci?ed in the universal serial bus speci?cation rev. 2.0 . 7.3 analog transceivers three sets of transceivers are embedded in the chip: two are used for downstream ports with usb connector type a; one is used for upstream port with usb connector type b. the integrated transceivers are compliant with the universal serial bus speci?cation rev. 2.0 . they interface directly with the usb connectors and cables through external termination resistors. 7.4 philips serial interface engine (sie) the philips sie implements the full usb protocol layer. it is completely hardwired for speed and needs no ?rmware intervention. the functions of this block include: synchronization pattern recognition, parallel/serial conversion, bit (de)stuf?ng, crc checking/generation, packet identi?er (pid) veri?cation/generation, address recognition, handshake evaluation/generation. there are separate sies in the hc and the dc. 7.5 softconnect the connection to the usb is accomplished by bringing d + (for full-speed usb devices) high through a 1.5 k w pull-up resistor. in the isp1161a1 dc, the 1.5 k w pull-up resistor is integrated on-chip and is not connected to v cc by default. the connection is established through a command sent by the external/system microcontroller. this allows the system microcontroller to complete its initialization sequence before deciding to establish connection with the usb. re-initialization of the usb connection can also be performed without disconnecting the cable. the isp1161a1 dc will check for usb v bus availability before the connection can be established. v bus sensing is provided through pin d_vbus. remark: the tolerance of the internal resistors is 25 %. this is higher than the 5 % tolerance speci?ed by the usb speci?cation. however, the overall voltage speci?cation for the connection can still be met with a good margin. the decision to make use of this feature lies with the usb equipment designer.
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 12 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7.6 goodlink indication of a good usb connection is provided at pin gl through goodlink technology. during enumeration, the led indicator will blink on momentarily. when the dc has been successfully enumerated (the device address is set), the led indicator will remain permanently on. upon each successful packet transfer (with ack) to and from the isp1161a1 the led will blink off for 100 ms. during suspend state the led will remain off. this feature provides a user-friendly indication of the status of the usb device, the connected hub and the usb traf?c. it is a useful ?eld diagnostics tool for isolating faulty equipment. it can therefore help to reduce ?eld support and hotline overhead. 8. microprocessor bus interface 8.1 programmed i/o (pio) addressing mode a generic pio interface is de?ned for speed and ease-of-use. it also allows direct interfacing to most microcontrollers. to a microcontroller, the isp1161a1 appears as a memory device with a 16-bit data bus and uses only two address lines: a1 and a0 to access the internal control registers and fifo buffer ram. therefore, the isp1161a1 occupies only four i/o ports or four memory locations of a microprocessor. external microprocessors can read from or write to the isp1161a1 internal control registers and fifo buffer ram through the programmed i/o (pio) operating mode. figure 8 shows the programmed i/o interface between a microprocessor and an isp1161a1. 8.2 dma mode the isp1161a1 also provides dma mode for external microprocessors to access its internal fifo buffer ram. data can be transferred by dma operation between a microprocessors system memory and the isp1161a1 internal fifo buffer ram. remark: the dma operation must be controlled by the external microprocessor system dma controller (master). fig 8. programmed i/o interface between a microprocessor and an isp1161a1. 004aaa178 d [ 15:0 ] rd wr cs a2 irq2 micro- processor isp1161a1 d [ 15:0 ] m p bus i/f rd wr cs a1 a1 irq1 a0 int1 int2
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 13 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. figure 9 shows the dma interface between a microprocessor system and the isp1161a1. the isp1161a1 provides two dma channels: ? dma channel 1 (controlled by dreq1, d a ck1 signals) is for the dma transfer between a microprocessors system memory and the isp1161a1 hc internal fifo buffer ram. ? dma channel 2 (controlled by dreq2, d a ck2 signals) is for the dma transfer between a microprocessor system memory and the isp1161a1 dc internal fifo buffer ram. the eot signal is an external end-of-transfer signal used to terminate the dma transfer. some microprocessors may not have this signal. in this case, the isp1161a1 provides an internal eot signal to terminate the dma transfer as well. setting the hcdmacon?guration register (21h to read, a1h to write) enables the isp1161a1 hc internal dma counter for dma transfer. when the dma counter reaches the value set in the hctransfercounter register (22h to read, a2h to write), an internal eot signal will be generated to terminate the dma transfer. 8.3 control register access by pio mode 8.3.1 i/o port addressing ta b l e 3 shows the isp1161a1 i/o port addressing. complete decoding of the i/o port address should include the chip select signal cs and the address lines a1 and a0. however, the direction of the access of the i/o ports is controlled by the rd and wr signals. when rd is low, the microprocessor reads data from the isp1161a1 data port. when wr is low, the microprocessor writes a command to the command port, or writes data to the data port. fig 9. dma interface between a microprocessor and an isp1161a1. 004aaa179 d [ 15:0 ] rd wr dack1 dreq1 eot micro- processor isp1161a1 d [ 15:0 ] m p bus i/f rd wr dack1 dreq1 dack2 dreq2 dack2 dreq2 eot table 3: i/o port addressing port cs a1,a0 (bin) access data bus width (bits) description 0 0 00 r/w 16 hc data port 1 0 01 w 16 hc command port 2 0 10 r/w 16 dc data port 3 0 11 w 16 dc command port
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 14 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. figure 10 and figure 11 illustrate how an external microprocessor accesses the isp1161a1 internal control registers. 8.3.2 register access phases the isp1161a1 register structure is a command-data register pair structure. a complete register access cycle comprises a command phase followed by a data phase. the command (also known as the index of a register) points the isp1161a1 to the next register to be accessed. a command is 8 bits long. on a microprocessors 16-bit data bus, a command occupies the lower byte, with the upper byte ?lled with zeros. figure 12 shows a complete 16-bit register access cycle for the isp1161a1. the microprocessor writes a command code to the command port, and then reads or writes the data word from or to the data port. take the example of a microprocessor attempting to read the isp1161a1s id, which is saved in the hcs hcchipid register (index 27h, read only). the 16-bit register access cycle is therefore: 1. microprocessor writes the command code of 27h (0027h in 16-bit width) to the hc command port 2. microprocessor reads the data word of the chips id (6110h for engineering sample; version one) from the hc data port. when a1 = 0, the microprocessor accesses the hc. when a1 = 1, the microprocessor accesses the dc. fig 10. microprocessor access to a hc or a dc via an automux switch. when a0 = 0, the microprocessor accesses the data port. when a0 = 1, the microprocessor accesses the command port. fig 11. microprocessor access to internal control registers. mgt935 m p bus i/f host bus i/f device bus i/f automux dc/hc a1 0 1 mgt936 cmd/data switch commands control registers command register data port a0 command port . . . host or device bus i/f 1 0
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 15 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. most of the isp1161a1 internal control registers are 16-bit wide. some of the internal control registers, however, have 32-bit width. figure 13 shows how the 32-bit internal control register is accessed. the complete cycle of accessing a 32-bit register consists of a command phase followed by two data phases. in the two data phases, the microprocessor ?rst reads or writes the lower 16-bit data, followed by the upper 16-bit data. to further describe the complete access cycles of the internal control registers, the status of some pins of the microprocessor bus interface are shown in figure 14 and figure 15 for the hc and the dc respectively. fig 12. 16-bit register access cycle. fig 13. 32-bit register access cycle. fig 14. accessing hc control registers. mgt937 read/write data (16 bits) 16-bit register access cycle t write command (16 bits) mgt938 read/write data (lower 16 bits) 32-bit register access cycle t read/write data (upper 16 bits) write command (16 bits) a1, a0 wr cs 01 00 00 mgt939 d [ 15:0 ] rd hc command code hc register data (upper word) hc register data read read write write write read read write write (lower word)
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 16 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.4 fifo buffer ram access by pio mode since the isp1161a1 internal memory is structured as a fifo buffer ram, the fifo buffer ram is mapped to dedicated register ?elds. therefore, accessing the internal fifo buffer ram is similar to accessing the internal control registers in multiple data phases. figure 16 shows a complete access cycle of the hc internal fifo buffer ram. for a write cycle, the microprocessor ?rst writes the fifo buffer rams command code to the command port, and then writes the data words one by one to the data port until half of the transfers byte count is reached. the hctransfercounter register (22h to read, a2h to write) is used to specify the byte count of a fifo buffer rams read cycle or write cycle. every access cycle must be in the same access direction. the read cycle procedure is similar to the write cycle. for access to the dc fifo buffer ram, see section 13 . fig 15. accessing dc control registers. a1, a0 wr cs 11 10 10 mgt940 d [ 15:0 ] rd dc command code dc register data (upper word) dc register data read read write write write read read write write (lower word) fig 16. internal fifo buffer ram access cycle. mgt941 read/write data #1 (16 bits) fifo buffer ram access cycle (transfer counter = 2n) t read/write data #2 (16 bits) read/write data #n (16 bits) write command (16 bits)
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 17 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.5 fifo buffer ram access by dma mode the dma interface between a microprocessor and the isp1161a1 is shown in figure 9 . when doing a dma transfer, at the beginning of every burst the isp1161a1 outputs a dma request to the microprocessor via the dreq pin (dreq1 for hc, dreq2 for dc). after receiving this signal, the microprocessor will reply with a dma acknowledge via the d a ck pin ( d a ck1 for hc, d a ck2 for dc), and at the same time, execute the dma transfer through the data bus. in the dma mode, the microprocessor must issue a read or write signal to the isp1161a1 rd or wr pin. the isp1161a1 will repeat the dma cycles until it receives an eot signal to terminate the dma transfer. the isp1161a1 supports both external and internal eot signals. the external eot signal is received as input on pin eot, and generally comes from the external microprocessor. the internal eot signal is generated by the isp1161a1 internally. to select either eot method, set the appropriate dma con?guration register (see section 10.4.2 and section 13.1.6 ). for example, for the hc, setting dmacounterselect of the hcdmacon?guration register (21h to read, a1h to write) to logic 1 will enable the dma counter for dma transfer. when the dma counter reaches the value of the hctransfercounter register, the internal eot signal will be generated to terminate the dma transfer. the isp1161a1 supports either single-cycle dma operation or burst mode dma operation; see figure 17 and figure 18 . n = 1/2 byte count of transfer data. fig 17. dma transfer in single-cycle mode. 004aaa103 dreq dack d [ 15:0 ] eot data #1 data #2 data #n rd or wr
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 18 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. in both ?gures, the hardware is con?gured such that dreq is active high and d a ck is active low. 8.6 interrupts the isp1161a1 has separate interrupt request pins for the usb hc (int1) and the usb dc (int2). 8.6.1 pin con?guration the interrupt output signals have four con?guration modes: mode 0 level trigger, active low (default at power-up) mode 1 level trigger, active high mode 2 edge trigger, active low mode 3 edge trigger, active high. figure 19 shows these four interrupt con?guration modes. they are programmable via the hchardwarecon?guration register (see section 10.4.1 ), which is also used to disable or enable the signals. n = 1/2 byte count of transfer data, k = number of cycles/burst. fig 18. dma transfer in burst mode. 004aaa104 data #1 data #k data #2k data #n data #(k + 1) data #(n - k + 1) dreq dack d [ 15:0 ] eot rd or wr
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 19 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.6.2 hcs interrupt output pin (int1) to program the four con?guration modes of the hcs interrupt output signal (int1), set bits interruptpintrigger and interruptoutputpolarity of the hchardwarecon?guration register (20h to read, a0h to write). bit interruptpinenable is used as the master enable setting for pin int1. int1 has many associated interrupt events, as shown as in figure 20 . the interrupt events of the hc m pinterrupt register (24h to read, a4h to write) changes the status of pin int1 when the corresponding bits of the hc m pinterruptenable register (25h to read, a5h to write) and pin int1s global enable bit (interruptpinenable of the hchardwarecon?guration register) are all set to enable status. however, events that come from the hcinterruptstatus register (03h to read, 83h to write) affect only bit opr_reg of the hc m pinterrupt register. they cannot directly change the status of pin int1. fig 19. interrupt pin operating modes. mgt944 int active int active clear or disable int mode 1 level triggered, active high int int 166 ns mode 2 edge triggered, active low int active int 166 ns mode 3 edge triggered, active high int active clear or disable int mode 0 level triggered, active low int
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 20 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. there are two groups of interrupts represented by group 1 and group 2 in figure 20 . a pair of registers control each group. group 2 contains six possible interrupt events (recorded in the hcinterruptstatus register). on occurrence of any of these events, the corresponding bit would be set to logic 1; and if the corresponding bit in the hcinterruptenable register is also logic 1, the 6-input or gate would output a logic 1. this output is and-ed with the value of mie (bit 31 of hcinterruptenable). logic 1 at the and gate will cause bit opr in the hc m pinterrupt register to be set to logic 1. group 1 contains six possible interrupt events, one of which is the output of group 2 interrupt sources. the hc m pinterrupt and hc m pinterruptenable registers work in the same way as the hcinterruptstatus and hcinterruptenable registers in the interrupt group 2. the output from the 6-input or gate is connected to a latch, which is controlled by interruptpinenable (bit 0 of the hchardwarecon?guration register). in the event in which the software wishes to temporarily disable the interrupt output of the isp1161a1 host controller, the following procedure should be followed: 1. make sure that bit interruptpinenable in the hchardwarecon?guration register is set to logic 1. 2. clear all bits in the hc m pinterrupt register. 3. set bit interruptpinenable to logic 0. fig 20. hc interrupt logic. mgt945 sofitlint atlint alleotinterrupt opr_reg hcsuspended hcpinterrupt register hcinterruptenable register hcinterruptstatus register clkready rhsc fno ue rd sf so rhsc fno ue rd sf so mie or sofitlint atlint alleotinterrupt opr_reg hcsuspended hcpinterruptenable register clkready or latch int1 group 2 interruptpinenable hchardwareconfiguration register group 1 le
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 21 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. to re-enable the interrupt generation: 1. set all bits in the hc m pinterrupt register. 2. set bit interruptpinenable to logic 1. remark: bit interruptpinenable in the hchardwarecon?guration register latches the interrupt output. when this bit is set to logic 0, the interrupt output will remain unchanged, regardless of any operations on the interrupt control registers. if int1 is asserted, and the hcd wishes to temporarily mask off the int signal without clearing the hc m pinterrupt register, the following procedure should be followed: 1. make sure that bit interruptpinenable is set to logic 1. 2. clear all bits in the hc m pinterruptenable register. 3. set bit interruptpinenable to logic 0. to re-enable the interrupt generation: 1. set all bits in the hc m pinterruptenable register according to the hcd requirements. 2. set bit interruptpinenable to logic 1. 8.6.3 dc interrupt output pin (int2) the four con?guration modes of dcs interrupt output pin int2 can also be programmed by setting bits intpol and intlvl of the dchardwarecon?guration register (bbh to read, bah to write). bit intena of the dcmode register (b9h to read, b8h to write) is used to enable pin int2. figure 21 shows the relationship between the interrupt events and pin int2. each of the indicated usb events is logged in a status bit of the dcinterrupt register. corresponding bits in the dcinterruptenable register determine whether or not an event will generate an interrupt. interrupts can be masked globally by means of bit intena of the dcmode register (see ta b l e 8 1 ). the active level and signalling mode of the int output is controlled by bits intpol and intlvl of the dchardwarecon?guration register (see ta b l e 8 3 ). default settings after reset are active low and level mode. when pulse mode is selected, a pulse of 166 ns is generated when the or-ed combination of all interrupt bits changes from logic 0 to logic 1. bits reset, resume, sp_eot, eot and sof are cleared upon reading the dcinterrupt register. the endpoint bits (ep0out to ep14) are cleared by reading the associated dcendpointstatus register. bit bustatus follows the usb bus status exactly, allowing the ?rmware to get the current bus status when reading the dcinterrupt register. setup and out token interrupts are generated after the dc has acknowledged the associated data packet. in bulk transfer mode, the dc will issue interrupts for every ack received for an out token or transmitted for an in token.
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 22 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. in isochronous mode, an interrupt is issued upon each packet transaction. the ?rmware must take care of timing synchronization with the host. this can be done via the pseudo start-of-frame (psof) interrupt, enabled via bit iepsof in the dcinterruptenable register. if a start-of-frame is lost, psof interrupts are generated every 1 ms. this allows the ?rmware to keep data transfer synchronized with the host. after 3 missed sof events, the dc will enter suspend state. an alternative way of handling isochronous data transfer is to enable both the sof and the psof interrupts and disable the interrupt for each isochronous endpoint. interrupt control: bit intena in the dcmode register is a global enable/disable bit. the behavior of this bit is given in figure 22 . fig 21. dc interrupt logic. pin int2: high = de-assert; low = assert (individual interrupts are enabled). fig 22. behavior of bit intena. mgt946 reset suspnd resume sof ep14 ... ep0in . . . . . . . . . . . . ep0out eot ierst dcinterrupt register dcinterruptenable register iesusp ieresm iesof iep14 ... iep0in iep0out ieeot dcmode register intena int2 latch le int2 pin 004aaa198 intena = 0 sof asserted intena = 1 sof asserted intena = 0 (during this time, an interrupt event occurs. for example, sof asserted.) a b c
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 23 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. event a (see figure 22 ): when an interrupt event occurs (for example, sof interrupt) with bit intena set to logic 0, an interrupt will not be generated at pin int2. however, it will be registered in the corresponding dcinterrupt register bit. event b (see figure 22 ): when bit intena is set to logic 1, pin int2 is asserted because bit sof in the dcinterrupt register is already asserted. event c (see figure 22 ): if the ?rmware sets bit intena to logic 0, pin int2 will still be asserted. the bold dashed line shows the desired behavior of pin int2. de-assertion of pin int2 can be achieved in the following manner. bits[23:8] of the dcinterrupt register are endpoint interrupts. these interrupts are cleared on reading their respective dcendpointstatus register. bits[7:0] of the dcinterrupt register are bus status and eot interrupts that are cleared on reading the dcinterrupt register. make sure that bit intena is set to logic 1 when you perform the clear interrupt commands. for more information on interrupt control, see section 13.1.3 , section 13.1.5 and section 13.3.6 .
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 24 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9. usb host controller (hc) 9.1 hcs four usb states the isp1161a1 usb hc has four usb states - usboperational, usbreset, usbsuspend, and usbresume - that de?ne the hcs usb signaling and bus states responsibilities. the usb states are re?ected in the hostcontrollerfunctionalstate ?eld of the hccontrol register (01h to read, 81h to write), which is located at bits 7 and 6 of the register. the host controller driver (hcd) can perform only the usb state transitions shown in figure 23 . remark: the software reset in figure 23 is not caused by the hcsoftwarereset command. it is caused by the hostcontrollerreset ?eld of the hccommandstatus register (02h to read, 82h to write). 9.2 generating usb traf?c usb traf?c can be generated only when the isp1161a1 usb hc is in the usboperational state. therefore, the hcd must set the hostcontrollerfunctionalstate ?eld of the hccontrol register before generating usb traf?c. a simplistic ?ow diagram showing when and how to generate usb traf?c is shown in figure 24 . for more detail, refer to the usb speci?cation revision 2.0 about the protocol and isp1161a1 usb hc register usage. fig 23. isp1161a1 hc usb states. mgt947 usboperational usbsuspend usbresume usbresume write or remote wake-up usbreset usboperational write usboperational write usbsuspend write usbreset write usbreset write usbreset write hardware or software reset
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 25 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. description of figure 24 : 1. reset this includes hardware reset by pin reset and software reset by the hcsoftwarereset command (a9h). the reset function will clear all the hcs internal control registers to their reset status. after reset, the hcd must initialize the isp1161a1 usb hc by setting some registers. 2. initialize hc it includes: a. setting the physical size for the hcs internal fifo buffer ram by setting the hcitlbufferlength register (2ah to read, aah to write) and the hcatlbufferlength register (2bh to read, abh to write) b. setting the hchardwarecon?guration register according to requirements c. clearing interrupt events, if required d. enabling interrupt events, if required e. setting the hcfminterval register (0dh to read, 8dh to write) f. setting the hcs root hub registers g. setting the hccontrol register to move the hc into usboperational state see also section 9.5 . 3. entry the normal entry point. the microprocessor returns to this point when there are hc requests. 4. need usb traf?c usb devices need the hc to generate usb traf?c when they have usb traf?c requests such as: a. connecting to or disconnecting from the downstream ports b. issuing the resume signal to the hc to generate usb traf?c, the hcd must enter the usb transaction loop. 5. prepare ptd data in microprocessors system ram the communication between the hcd and the isp1161a1 hc is in the form of philips transfer descriptor (ptd) data. the ptd data provides usb traf?c information about the commands, status, and usb data packets. fig 24. isp1161a1 hc usb transaction loop. mgt948 need usb traffic? prepare ptd data in m p system ram initialize hc transfer ptd data into hc fifo buffer ram hc performs usb transactions via usb bus i/f hc informs hcd of usb traffic results hc interprets ptd data exit entry hc state = usboperational no yes reset
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 26 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. the physical storage media of ptd data for the hcd is the microprocessors system ram. for the isp1161a1 hc, the storage media is the internal fifo buffer ram. the hcd prepares ptd data in the microprocessor system ram for transfer to the isp1161a1 hc internal fifo buffer ram. 6. transfer ptd data into hcs fifo buffer ram when ptd data is ready in the microprocessors system ram, the hcd must transfer the ptd data from the microprocessors system ram into the isp1161a1 internal fifo buffer ram. 7. hc interprets ptd data the hc determines what usb transactions are required based on the ptd data that has been transferred into the internal fifo buffer ram. 8. hc performs usb transactions via usb bus interface the hc performs the usb transactions with the speci?ed usb device endpoint through the usb bus interface. 9. hc informs hcd of the usb traf?c results the usb transaction status and the feedback from the speci?ed usb device endpoint will be put back into the isp1161a1 hc internal fifo buffer ram in ptd data format. the hcd can read back the ptd data from the internal fifo buffer ram. 9.3 ptd data structure the philips transfer descriptor (ptd) data structure provides communication between the hcd and the isp1161a1 usb hc. the ptd data contains information required by the usb traf?c. ptd data consists of a ptd followed by its payload data, as shown in figure 25 . the ptd data structure is used by the hc to de?ne a buffer of data that will be moved to or from an endpoint in the usb device. this data buffer is set up for the current frame (1 ms frame) by the hcd. the payload data for every transfer in the frame must have a ptd as a header to describe the characteristics of the transfer. ptd data is dword (double-word or 4-byte) aligned. fig 25. ptd data in fifo buffer ram. mgt949 ptd fifo buffer ram payload data ptd data #1 ptd payload data payload data ptd ptd data #2 ptd data #n top bottom
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 27 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.3.1 ptd data header de?nition the ptd forms the header of the ptd data. it tells the hc the transfer type, where the payload data should go, and the actual size of the payload data. a ptd is an 8 byte data structure that is very important for hcd programming. table 4: philips transfer descriptor (ptd): bit allocation bit 7 6 5 4 3 2 1 0 byte 0 actualbytes[7:0] byte 1 completioncode[3:0] active toggle actualbytes[9:8] byte 2 maxpacketsize[7:0] byte 3 endpointnumber[3:0] last speed maxpacketsize[9:8] byte 4 totalbytes[7:0] byte 5 reserved b5_5 reserved directionpid[1:0] totalbytes[9:8] byte 6 format functionaddress[6:0] byte 7 reserved
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 28 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. table 5: philips transfer descriptor (ptd): bit description symbol access description actualbytes[9:0] r/w contains the number of bytes that were transferred for this ptd completioncode[3:0] r/w 0000 noerror general td or isochronous data packet processing completed with no detected errors. 0001 crc last data packet from endpoint contained a crc error. 0010 bitstuf?ng last data packet from endpoint contained a bit stuf?ng violation. 0011 datatogglemismatch last packet from endpoint had data toggle pid that did not match the expected value. 0100 stall td was moved to the done queue because the endpoint returned a stall pid. 0101 devicenotresponding device did not respond to token (in) or did not provide a handshake (out). 0110 pidcheckfailure check bits on pid from endpoint failed on data pid (in) or handshake (out) 0111 unexpectedpid received pid was not valid when encountered or pid value is not de?ned. 1000 dataoverrun the amount of data returned by the endpoint exceeded either the size of the maximum data packet allowed from the endpoint (found in the maxpacketsize ?eld of ed) or the remaining buffer size. 1001 dataunderrun the endpoint returned is less than maxpacketsize and that amount was not suf?cient to ?ll the speci?ed buffer. 1010 reserved - 1011 reserved - 1100 bufferoverrun during an in, the hc received data from an endpoint faster than it could be written to system memory. 1101 bufferunderrun during an out, the hc could not retrieve data from the system memory fast enough to keep up with the usb data rate. active r/w set to logic 1 by ?rmware to enable the execution of transactions by the hc. when the transaction associated with this descriptor is completed, the hc sets this bit to logic 0, indicating that a transaction for this element will not be executed when it is next encountered in the schedule. toggle r/w used to generate or compare the data pid value (data0 or data1). it is updated after each successful transmission or reception of a data packet. maxpacketsize[9:0] r the maximum number of bytes that can be sent to or received from the endpoint in a single data packet. endpointnumber[3:0] r usb address of the endpoint within the function. last r last ptd of a list (itl or atl). logic 1 indicates that the ptd is the last ptd. speed r speed of the endpoint: 0 full speed 1 low speed totalbytes[9:0] r speci?es the total number of bytes to be transferred with this data structure. for bulk and control only, this can be greater than maxpacketsize.
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 29 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.4 hc internal fifo buffer ram structure 9.4.1 partitions according to the universal serial bus speci?cation rev. 2.0 , there are four types of usb data transfers: control, bulk, interrupt and isochronous. the hcs internal fifo buffer ram has a physical size of 4 kbytes. this internal fifo buffer ram is used for transferring data between the microprocessor and usb peripheral devices. this on-chip buffer ram can be partitioned into two areas: acknowledged transfer list (atl) buffer and isochronous (iso) transfer list (itl) buffer. the itl buffer is a ping-pong structured fifo buffer ram that is used to keep the payload data and their ptd header for isochronous transfers. the atl buffer is a non ping-pong structured fifo buffer ram that is used for the other three types of transfers. the itl buffer can be further partitioned into itl0 and itl1 for the ping-pong structure. the itl0 buffer and itl1 buffer always have the same size. the microprocessor can put iso data into either the itl0 buffer or the itl1 buffer. when the microprocessor accesses an itl buffer, the hc can take over the other itl buffer at the same time. this architecture improves the iso transfer performance. the hcd can assign the logical size for the atl buffer and itl buffers at any time, but normally at initialization after power-on reset. this is done by setting the hcatlbufferlength register (2bh to read, abh to write) and hcitlbufferlength register (2ah to read, aah to write). the total buffer length cannot exceed the maximum ram size of 4 kbytes (atl buffer + itl buffer). figure 26 shows the partitions of the internal fifo buffer ram. when assigning buffer ram sizes, follow this formula: atl buffer length + 2 (itl buffer size) 1000h (that is, 4 kbytes) where: itl buffer size = itl0 buffer length = itl1 buffer length the following assignments are examples of legal uses of the internal fifo buffer ram: ? atl buffer length = 800h, itl buffer length = 400h. this is the maximum use of the internal fifo buffer ram. directionpid[1:0] r 00 setup 01 out 10 in 11 reserved b5_5 r/w this bit is logic 0 at power-on reset. when this feature is not used, software used for the isp1161a1 is the same for the isp1160 and the isp1161. when this bit is set to logic 1 in this ptd for interrupt endpoint transfer, only one ptd usb transaction will be sent out in 1 ms. format r the format of this data structure. if this is a control, bulk or interrupt endpoint, then format = 0. if this is an isochronous endpoint, then format = 1. functionaddress[6:0] r this is the usb address of the function containing the endpoint that this ptd refers to. table 5: philips transfer descriptor (ptd): bit description continued symbol access description
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 30 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. ? atl buffer length = 400h, itl buffer length = 200h. this is insuf?cient use of the internal fifo buffer ram. ? atl buffer length = 1000h, itl buffer length = 0h. this will use the internal fifo buffer ram for only atl transfers. the actual requirement for the buffer ram need not reach the maximum size. you can make your selection based on your application. the following are some calculations of the iso_a or iso_b space for a frame of data: ? maximum number of useful data sent during one usb frame is 1280 bytes (20 iso packets of 64 bytes). the total ram size needed is: 20 8 + 1280 = 1440 bytes. ? maximum number of packets for different endpoints sent during one usb frame is 150 (150 iso packets of 1 byte). the total ram size needed is: 150 8 + 150 1 = 1350 bytes. ? the ping buffer ram (itl0) and the pong buffer ram (itl1) have a maximum size of 2 kbytes each. all data needed for one frame can be stored in the ping or the pong buffer ram. when the embedded system wants to initiate a transfer to the usb bus, the data needed for one frame is transferred to the atl buffer or itl buffer. the microprocessor detects the buffer status through the interrupt routines. when the hcbufferstatus register (2ch to read only) indicates that the buffer is empty, then the microprocessor writes data into the buffer. when the hcbufferstatus register indicates that the buffer is full, the data is ready on the buffer, and the microprocessor needs to read data from the buffer. during every 1 ms, there might be many events to generate interrupt requests to the microprocessor for data transfer or status retrieval. however, each of the interrupt types de?ned in this speci?cation can be enabled or disabled by setting the hc m pinterruptenable register bits accordingly. fig 26. hc internal fifo buffer ram partitions. mgt950 not used atl buffer itl0 top bottom itl1 iso_a fifo buffer ram iso_b control/bulk/interrupt data programmable sizes 4 kbytes itl buffer atl
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 31 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. the data transfer can be done via the pio mode or the dma mode. the data transfer rate can go up to 15 mbyte/s. in the dma operation, the single-cycle or multi-cycle burst modes are supported. multi-cycle burst modes of 1, 4, or 8 cycles per burst is supported for the isp1161a1. 9.4.2 data organization ptd data is used for every data transfer between a microprocessor and the usb bus, and the ptd data resides in the buffer ram. for an out or setup transfer, the payload data is placed just after the ptd, after which the next ptd is placed. for an in transfer, ram space is reserved for receiving a number of bytes that is equal to the total bytes of the transfer. after this, the next ptd and its payload data are placed (see figure 27 ). remark: the ptd is de?ned for both atl and itl type data transfers. for itl, the ptd data is put into itl buffer ram, and the isp1161a1 takes care of the ping-pong action for the itl buffer ram access. the ptd data (ptd header and its payload data) is a structure of dword (double- word or 4-byte) alignment. this means that the memory address is organized in blocks of 4 bytes. therefore, the ?rst byte of every ptd and the ?rst byte of every payload data are located at an address which is a multiple of 4. figure 28 illustrates an example in which the ?rst payload data is 14 bytes long, meaning that the last byte of the payload data is at the location 15h. the next addresses (16h and 17h) are not multiples of 4. therefore, the ?rst byte of the next ptd will be located at the next multiple-of-four address, 18h. fig 27. buffer ram data organization. mgt952 ptd of out transfer ram buffer payload data of out transfer ptd of in transfer empty space for in total data ptd of out transfer payload data of out transfer top bottom 000h 7ffh
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 32 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.4.3 operation and c program example figure 29 shows the block diagram for internal fifo buffer ram operations in the pio mode. the isp1161a1 provides one register as the access port for each buffer ram. for the itl buffer ram, the access port is the itlbufferport register (40h to read, c0h to write). for the atl buffer ram, the access port is the atlbufferport register (41h to read, c1h to write). the buffer ram is an array of bytes (8 bits) while the access port is a 16-bit register. therefore, each read/write operation on the port accesses two consecutive memory locations, incrementing the pointer of the internal buffer ram by two. the lower byte of the access port register corresponds to the data byte at the even location of the buffer ram, and the upper byte corresponds to the next data byte at the odd location of the buffer ram. regardless of the number of data bytes to be transferred, the command code must be issued merely once, and it will be followed by a number of accesses of the data port (see section 8.4 ). when the pointer of the buffer ram reaches the value of the hctransfercounter register, an internal eot signal will be generated to set bit 2, alleotinterrupt, of the hc m pinterrupt register and update the hcbufferstatus register, to indicate that the whole data transfer has been completed. for itl buffer ram, every start of frame (sof) signal (1 ms) will cause toggling between itl0 and itl1, but this depends on the buffer status. if both itl0bufferfull and itl1bufferfull of the hcbufferstatus register are already logic 1, meaning that both itl0 and itl1 buffer rams are full, the toggling will not happen. in this case, the microprocessor will always have access to itl1. fig 28. ptd data with dword alignment in buffer ram. mgt953 payload data (14 bytes) ptd (8 bytes) ptd (8 bytes) 00h top 08h 15h 18h 20h payload data ram buffer
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 33 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. following is an example of a c program that shows how to write data into the atl buffer ram. the total number of data bytes to be transferred is 80 (decimal) that will be set into the hctransfercounter register as 50h. the data consists of four types of ptd data: 1. the ?rst ptd header (in) is 8 bytes, followed by 16 bytes of space reserved for its payload data; 2. the second ptd header (in) is also 8 bytes, followed by 8 bytes of space reserved for its payload data; 3. the third ptd header (out) is 8 bytes, followed by 16 bytes of payload data with values beginning from 0h to fh incrementing by 1; 4. the fourth ptd header (out) is also 8 bytes, followed by 8 bytes of payload data with values beginning from 0h to eh incrementing by 2. in all ptds, we have assigned device address as 5 and endpoint as 1. actualbytes is always zero (0). totalbytes equals the number of payload data bytes transferred, however, note that for bulk and control transfers, totalbytes can be greater than maxpacketsize. ta b l e 6 shows the results after running this program. fig 29. pio access to internal fifo buffer ram. mgt951 commands pointer automatically increments by 2 transfercounter bufferstatus bufferstatus internal eot itlbufferport atlbufferport atl buffer ram (8-bit width) control registers command register data port t eot 1 2 = 0 toggle command port m pinterrupt 22h/a2h 2ch 40h/c0h 41h/c1h 24h/a4h 000h 7ffh 001h itl1 buffer ram (8-bit width) 000h 3ffh 001h itl0 buffer ram (8-bit width) 000h 3ffh 001h a0 host bus i/f 1 0 (16-bit width) sof
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 34 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. if communication with a peripheral usb device is desired, however, the device should be connected to the downstream port and pass enumeration. // the example program for writing atl buffer ram #include #include #include // define register commands #define whctransfercounter 0x22 #define whcupinterrupt 0x24 #define whcatlbufferlength 0x2b #define whcbufferstatus 0x2c // define i/o port address for hc #define hcdataport 0x290 #define hccmdport 0x292 // declare external functions to be used unsigned int hcregread(unsigned int windex); void hcregwrite(unsigned int windex,unsigned int wvalue); void main(void) { unsigned int i; unsigned int wcount,wdata; // prepare ptd data to be written into hc atl buffer ram: unsigned int ptddata[0x28]= { 0x0800,0x1010,0x0810,0x0005, // ptd header for in token #1 // reserved space for payload data of in token #1 0x0000,0x0000,0x0000,0x0000, 0x0000,0x0000,0x0000,0x0000, 0x0800,0x1008,0x0808,0x0005, // ptd header for in token #2 // reserved space for payload data of in token #2 0x0000,0x0000,0x0000,0x0000, 0x0800,0x1010,0x0410,0x0005, // ptd header for out token #1 0x0100,0x0302,0x0504,0x0706, // payload data for out token #1 0x0908,0x0b0a,0x0d0c,0x0f0e, 0x0800,0x1808,0x0408,0x0005, // ptd header for out token #2 0x0200,0x0604,0x0a08,0x0e0c // payload data for out token #2 }; hcregwrite(whcupinterrupt,0x04); // clear eot interrupt bit // hcregwrite(whcitlbufferlength,0x0); hcregwrite(whcatlbufferlength,0x1000); // ram full use for atl // set the number of bytes to be transferred hcregwrite(whctransfercounter,0x50); wcount = 0x28; // get word count outport (hccmdport,0x00c1); // command for atl buffer write
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 35 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. // write 80 (0x50) bytes of data into atl buffer ram for (i=0;i philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 36 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. the end of the frame for full-speed and low-speed packets. by programming these ?elds, the effective usb bus usage can be changed. furthermore, the size of the itl buffers (hcitlbufferlength, 2ah to read, aah to write) is programmed. if a usb frame contains both iso and at packets, two interrupts will be generated per frame. one interrupt is issued concurrently with the sof. this interrupt (bit itlint is set in the hc m pinterrupt register) triggers reading and writing of the itl buffer by the microprocessor, after which the interrupt is cleared by the microprocessor. next the programmable atl interrupt (bit atlint is set in the hc m pinterrupt register) is issued, which triggers reading and writing of the atl buffer by the microprocessor, after which the interrupt is cleared by the microprocessor. if the microprocessor cannot handle the iso interrupt before the next iso interrupt, disrupted iso traf?c can result. to be able to send more than one packet to the same control or bulk endpoint in the same frame, the active bit and the totalbytes ?eld are introduced (see ta b l e 5 ). bit active is cleared only if all data of the philips transfer descriptor (ptd) has been transferred or if a transaction at that endpoint contained a fatal error. if all ptds of the atl are serviced, and the frame is not over yet, the hc starts looking for a ptd with bit active still set. if such a ptd is found and there is still enough time in this frame, another transaction is started on the usb bus for this endpoint. for iso processing, the hcd also has to take care of the hcbufferstatus register (2ch, read only) for the itl buffer ram operations. after the hcd writes iso data into itl buffer ram, the itl0bufferfull or itl1bufferfull bit (depending on whether it is itl0 or itl1) will be set to logic 1. after the hc processes the iso data in the itl buffer ram, the corresponding itl0bufferdone or itl1bufferdone bit will automatically be set to logic 1. the hcd can clear the buffer status bits by a read of the itl buffer ram. this must be done within the 1 ms frame from which itl0bufferdone or itl1bufferdone was set. for example, the hcd writes iso_a data into the itl0 buffer in the ?rst frame. this will cause the hcbufferstatus register to show that the itl0 buffer is full by setting bit itl0bufferfull to logic 1. at this stage, the hcd cannot write iso data into the itl0 buffer ram again. in the second frame, the hc will process the iso_a data in the itl0 buffer. at the same time, the hcd can write iso_b data into the itl1 buffer. when the next sof comes (the beginning of the third frame), both itl1bufferfull and itl0bufferdone are automatically set to logic 1. in the third frame, the hcd has to read at least two bytes (one word) of the itl0 buffer to clear both the itl0bufferfull and itl0bufferdone bits. if both are not cleared, when the next sof comes (the beginning of the fourth frame) the itl0bufferdone and itl0bufferfull bits will be cleared automatically. this also applies to the itl1 buffer because itl0 and itl1 are ping-pong structured buffers. to recover from this state, a power-on reset or software reset will have to be applied.
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 37 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.5.1 time domain behavior in example 1 ( figure 30 ), the microprocessor is fast enough to read back and download a scenario before the next interrupt. note that on the iso interrupt of frame n: ? the iso packet for frame n + 1 will be written ? the at packet for frame n + 1 will be written. in example 2 ( figure 31 ), the microprocessor is still busy transferring the at data when the iso interrupt of the next frame (n + 1) is raised. as a result, there will be no at traf?c in frame n + 1. the hc does not raise an at interrupt in frame n + 1. the at part is simply postponed until frame n + 2. on the at n + 2 interrupt, the transfer mechanism is back to the normal operation. this simple mechanism ensures, among other things, that control transfers are not dropped systematically from the usb in case of an overloaded microprocessor. in example 3 ( figure 32 ), the iso part is still being written while the start of frame (sof) of the next frame has occurred. this will result in unde?ned behavior for the iso data on the usb bus in frame n + 1 (depending on whether the exact timing data is corrupted or not). the hc should not raise an at interrupt in frame n + 1. fig 30. hc time domain behavior: example 1. mgt954 (frame n) (frame n + 1) (frame n + 2) (frame n + 3) read iso_a(n - 1) write iso_a(n + 1) sof read at(n) write at(n + 1) at interrupt traffic on usb iso interrupt fig 31. hc time domain behavior: example 2. mgt955 (frame n) (frame n + 1) (frame n + 2) (frame n + 3)
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 38 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.5.2 control transaction limitations the different phases of a control transfer (setup, data and status) should never be put in the same atl. 9.6 microprocessor loading the maximum amount of data that can be transferred for an endpoint in one frame is 1023 bytes. the number of usb packets that are needed for this batch of data depends on the maximum packet size that is speci?ed. the hcd has to schedule the transactions in a frame. on the other hand, the microprocessor must have the ability to handle the interrupts coming from the hc every 1 ms. it must also be able to do the scheduling for the next frame, reading the frame information from and writing the next frame information to the buffer ram in the time between the end of the current frame and the start of the next frame. 9.7 internal pull-down resistors for downstream ports there are four internal 15 k w pull-down resistors built into the isp1161a1 for the two downstream ports: two resistors for each port. these resistors are software selectable by programming bit 12 (2_downstreamport15kresistorsel) of the hchardwarecon?guration register (20h to read, a0h to write). when bit 12 is logic 0, external 15 k w pull-down resistors are used. when bit 12 is logic 1, internal 15 k w pull-down resistors are used. see figure 33 . this feature is a cost-saving option. however, the power-on reset default value of bit 12 is logic 0. if using the internal resistors, the hcd must set this bit status after every reset, because a reset action (hardware or software) will clear this bit. fig 32. hc time domain behavior: example 3. mgt956 (frame n) (frame n + 1) (frame n + 2) (frame n + 3)
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 39 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.8 oc detection and power switching control a downstream port provides 5 v power supply to v bus . the isp1161a1 has built-in hardware functions to monitor the downstream ports loading conditions and control their power switching. these hardware functions are implemented by the internal power switching control circuit and overcurrent detection circuit. h_psw1 and h_psw2 are power switching control output pins (active low, open-drain) for downstream ports 1 and 2, respectively. h_oc1 and h_oc2 are overcurrent detection input pins for downstream ports 1 and 2, respectively. figure 34 shows the isp1161a1 downstream port power management scheme (n represents the downstream port numbers, n=1or2). using either internal or external 15 k w resistors. fig 33. use of 15 k w pull-down resistors on downstream ports. 004aaa180 22 w 22 w bit 12 hchardware configuration isp1161a1 usb connector d - d + v bus internal 15 k w (2 ) external 15 k w (2 ) 47 pf (2 ) n represents the downstream port number ( n=1or2) fig 34. downstream port power management scheme. 004aaa181 1 3 0 reg bit 10 psw oc select oc detect regulator h_ocn h_pswn hc core c/l isp1161a1 v cc ( + 5 v or + 3.3 v) hchardware configuration
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 40 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.8.1 using an internal oc detection circuit the internal oc detection circuit can be used only when v cc (pin 56) is connected to a 5 v power supply. the hcd must set analogocenable, bit 10 of the hchardwarecon?guration register, to logic 1. an application using the internal oc detection circuit and internal 15 k w pull-down resistors is shown in figure 35 . in this example, the hcd must set both analogocenable and downstreamport15kresistorsel to logic 1. they are bit 10 and bit 12 of the hchardwarecon?guration register, respectively. when h_ocn detects an overcurrent status on a downstream port, h_pswn will output high, a logic 1 to turn off the 5 v power supply to the downstream port v bus . when there is no such condition, h_pswn will output low, a logic 0 to turn on the 5 v power supply to the downstream port v bus . in general applications, you can use a p-channel mosfet as the power switch for v bus . connect the 5 v power supply to the source of the p-channel mosfet, v bus to the drain, and h_pswn to the gate. call the voltage drop across the drain and source the overcurrent detection voltage (v oc ). for the internal overcurrent detection circuit, a voltage comparator has been incorporated with a nominal voltage threshold ( d v trip ) of 75 mv. when v oc exceeds v trip , h_pswn will output a high level, logic 1 to turn off the p-channel mosfet. if the p-channel mosfet has a r dson of 150 m w , the overcurrent threshold will be 500 ma. the selection of a p-channel mosfet with a different r dson will result in a different overcurrent threshold. n represents the downstream port number ( n=1or2) fig 35. using internal oc detection circuit. 004aaa182 atx 1 3 0 reg psw oc select oc detect regulator v cc h_ocn v oc = + 5 v - v bus h_pswn h_dmn h_dpn hc core c/l sie usb downstream port connector 15 k w (2 ) 47 pf (2 ) 22 w 22 w isp1161a1 v bus + 5 v p-ch mosfet bit 10 bit 12 hchardware configuration hchardware configuration
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 41 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.8.2 using an external oc detection circuit when v cc (pin 56) is connected to a 3.3 v instead of the 5 v power supply, the internal oc detection circuit cannot be used. an external oc detection circuit must be used instead. regardless of the v cc value, an external oc detection circuit can always be used. to use an external oc detection circuit, analogocenable, bit 10 of the hchardwarecon?guration register, should be logic 0. by default after reset, this bit is already logic 0; therefore, the hcd does not need to clear this bit. figure 36 shows how to use an external oc detection circuit. 9.9 suspend and wake-up 9.9.1 hc suspended state the hc can be put into suspended state by setting the hccontrol register (01h to read, 81h to write). see figure 23 for the hcs ?ow of usb state changes. n represents the downstream port number ( n=1or2) fig 36. using an external oc detection circuit. v o v i oc en v cc h_ocn h_pswn h_dmn h_dpn usb downstream port connector 47 pf (2 ) 22 w 22 w v bus + 3.3 v or + 5 v + 5 v external oc detect 004aaa183 atx 1 3 0 reg psw oc select oc detect regulator hc core c/l sie 15 k w (2 ) isp1161a1 bit 10 bit 12 hchardware configuration hchardware configuration
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 42 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. in the suspended state, the device will consume considerably less power by turning off the internal 48 mhz clock, pll and crystal, and setting the internal regulator to power-down mode. the isp1161a1 suspend and resume clock scheme is shown in figure 37 . remark: the isp1161a1 can only be put into a fully suspended state only after both the hc and the dc go into the suspend state. at this point, the crystal can be turned off and the internal regulator can be put into power-down mode. pin h_suspend is the sensing output pin for the hcs suspended state. when the hc goes into the usbsuspend state, this pin will output a high level (logic 1). this pin is cleared to low (logic 0) level only when the hc is put into a usbreset state or usboperational state (refer to the hccontrol register bits 7 to 6, 01h to read, 81h to write). bit 11, suspendclknotstop, of the hchardwarecon?guration register (20h to read, a0h to write), de?nes if the hc internal clock is stopped or kept running when the hc goes into the usbsuspend state. after the hc enters the usbsuspend state for 1.3 ms, the internal clock will be stopped if bit suspendclknotstop is logic 0. 9.9.2 hc wake-up from suspended state there are three methods to wake up the hc from the usbsuspend state: hardware wake-up, software wake-up, and usb bus resume. they are described as follows: wake-up by pin h_wakeup: pins h_suspend and h_wakeup provide hardware wake-up, a way of remote wake-up control for the hc without the need to access the hc internal registers. h_wakeup is an external wake-up control input pin for the hc. after the hc goes into the usbsuspend state, it can be woken up by sending a high level pulse to pin h_wakeup. this will turn on the hcs internal clock, and set bit 6, clkready, of the hc m pinterrupt register (24h to read, a4h to write). under the usbsuspend state, once pin h_wakeup goes high, after 160 m s, the internal clock will be up. if pin h_wakeup continues to be high, then the internal clock will be kept running, and the microprocessor can set the hc into the usboperational state during this time. if h_wakeup goes low for more than 1.14 ms, the internal clock stops, and the hc goes back into the usbsuspend state. fig 37. isp1161a1 suspend and resume clock scheme. mgt958 on on xosc_6mhz (to dc pll) xosc on voltage regulator hc pll hc_clkok hc_rawclk48m hc_enableclock h_wakeup (pin) dc_enableclock cs (pin) hc_needclock pll_lock pll_clkout on digital clock switch hc core hc_clk48mout hchardware configuration bit 11 (suspendclknotstop)
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 43 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. wake-up by pin cs (software wake-up): during the usbsuspend state, an external microprocessor issues a chip select signal through pin cs. this method of access to the isp1161a1 internal registers is a software wake-up. wake-up by usb devices: for a usb bus resume, a usb device attached to the root hub port issues a resume signal to the hc through the usb bus, switching the hc from the usbsuspend state to the usbresume state. this will also set bit resumedetected of the hcinterruptstatus register (03h to read, 83h to write). no matter which method is used to wake up the hc from the usbsuspend state, the corresponding interrupt bits must be enabled before the hc goes into the usbsuspend state so that the microprocessor can receive the correct interrupt request to wake up the hc.
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 44 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10. hc registers the hc contains a set of on-chip control registers. these registers can be read or written by the host controller driver (hcd). the control and status register sets, frame counter register sets, and root hub register sets are grouped under the category of hc operational registers (32 bits). these operational registers are made compatible to openhci (host controller interface) operational registers. this allows the openhci hcd to be easily ported to the isp1161a1. reserved bits may be de?ned in future releases of this speci?cation. to ensure interoperability, the hcd must not assume that a reserved ?eld contains logic 0. furthermore, the hcd must always preserve the values of the reserved ?eld. when a r/w register is modi?ed, the hcd must ?rst read the register, modify the bits desired, and then write the register with the reserved bits still containing the original value. alternatively, the hcd can maintain an in-memory copy of previously written values that can be modi?ed and then written to the hc register. when a write to set or clear the register is performed, bits written to reserved ?elds must be logic 0. as shown in ta b l e 7 , the addresses (the commands for accessing registers) of these 32-bit operational registers are similar to the offsets de?ned in the ohci speci?cation with the addresses being equal to offset divided by 4. table 7: hc control register summary command (hex) register width reference functionality read write 00 - hcrevision 32 section 10.1.1 on page 45 hc control and status registers 01 81 hccontrol 32 section 10.1.2 on page 46 02 82 hccommandstatus 32 section 10.1.3 on page 47 03 83 hcinterruptstatus 32 section 10.1.4 on page 48 04 84 hcinterruptenable 32 section 10.1.5 on page 49 05 85 hcinterruptdisable 32 section 10.1.6 on page 51 0d 8d hcfminterval 32 section 10.2.1 on page 52 hc frame counter registers 0e - hcfmremaining 32 section 10.2.2 on page 53 0f - hcfmnumber 32 section 10.2.3 on page 54 11 91 hclsthreshold 32 section 10.2.4 on page 55 12 92 hcrhdescriptora 32 section 10.3.1 on page 56 hc root hub registers 13 93 hcrhdescriptorb 32 section 10.3.2 on page 58 14 94 hcrhstatus 32 section 10.3.3 on page 59 15 95 hcrhportstatus[1] 32 section 10.3.4 on page 61 16 96 hcrhportstatus[2] 32 section 10.3.4 on page 61 20 a0 hchardwarecon?guration 16 section 10.4.1 on page 65 hc dma and interrupt control registers 21 a1 hcdmacon?guration 16 section 10.4.2 on page 66 22 a2 hctransfercounter 16 section 10.4.3 on page 67 24 a4 hc m pinterrupt 16 section 10.4.4 on page 68 25 a5 hc m pinterruptenable 16 section 10.4.5 on page 69
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 45 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.1 hc control and status registers 10.1.1 hcrevision register (r: 00h) code (hex): 00 read only 27 - hcchipid 16 section 10.5.1 on page 70 hc miscellaneous registers 28 a8 hcscratch 16 section 10.5.2 on page 71 - a9 hcsoftwarereset 16 section 10.5.3 on page 71 2a aa hcitlbufferlength 16 section 10.6.1 on page 72 hc buffer ram control registers 2b ab hcatlbufferlength 16 section 10.6.2 on page 72 2c - hcbufferstatus 16 section 10.6.3 on page 73 2d - hcreadbackitl0length 16 section 10.6.4 on page 74 2e - hcreadbackitl1length 16 section 10.6.5 on page 74 40 c0 hcitlbufferport 16 section 10.6.6 on page 75 41 c1 hcatlbufferport 16 section 10.6.7 on page 75 table 7: hc control register summary continued command (hex) register width reference functionality read write table 8: hcrevision register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset 00h access r bit 23 22 21 20 19 18 17 16 symbol reserved reset 00h access r bit 15 14 13 12 11 10 9 8 symbol reserved reset 00h access r bit 7 6 5 4 3 2 1 0 symbol rev[7:0] reset 10h access r table 9: hcrevision register: bit description bit symbol description 31 to 8 - reserved 7 to 0 rev[7:0] revision: this read-only ?eld contains the bcd representation of the version of the hci speci?cation that is implemented by this hc. for example, a value of 11h corresponds to version 1.1. all hc implementations that are compliant with this speci?cation will have a value of 10h.
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 46 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.1.2 hccontrol register (r/w: 01h/81h) the hccontrol register de?nes the operating modes for the hc. remotewakeupenable (rwe) is modi?ed only by the hcd. code (hex): 01 read code (hex): 81 write table 10: hccontrol register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset 00h access r/w bit 23 22 21 20 19 18 17 16 symbol reserved reset 00h access r/w bit 15 14 13 12 11 10 9 8 symbol reserved rwe rwc reserved reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol hcfs[1:0] reserved reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 11: hccontrol register: bit description bit symbol description 31 to 11 - reserved 10 rwe remotewakeupenable: this bit is used by the hcd to enable or disable the remote wake-up feature upon the detection of upstream resume signaling. when this bit is set and the resumedetected bit in hcinterruptstatus is set, a remote wake-up is signaled to the host system. setting this bit has no impact on the generation of hardware interrupt. 9rwc remotewakeupconnected: this bit indicates whether the hc supports remote wake-up signaling. if remote wake-up is supported and used by the system, it is the responsibility of system ?rmware to set this bit during post. the hc clears the bit upon a hardware reset but does not alter it upon a software reset. remote wake-up signaling of the host system is host-bus-speci?c, and is not described in this speci?cation.
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 47 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.1.3 hccommandstatus register (r/w: 02h/82h) the hccommandstatus register is used by the hc to receive commands issued by the hcd, and it also re?ects the hcs current status. to the hcd, it appears to be a write to set register. the hc must ensure that bits written as logic 1 become set in the register while bits written as logic 0 remain unchanged in the register. the hcd may issue multiple distinct commands to the hc without concern for corrupting previously issued commands. the hcd has normal read access to all bits. the schedulingoverruncount ?eld indicates the number of frames with which the hc has detected the scheduling overrun error. this occurs when the periodic list does not complete before eof. when a scheduling overrun error is detected, the hc increments the counter and sets the schedulingoverrun ?eld in the hcinterruptstatus register. code (hex): 02 read code (hex): 82 write 8 - reserved 7 to 6 hcfs hostcontrollerfunctionalstate for usb: 00b usbreset 01b usbresume 10b usboperational 11b usbsuspend a transition to usboperational from another state causes start-of-frame (sof) generation to begin 1 ms later. the hcd determines whether the hc has begun sending sofs by reading the startofframe ?eld of hcinterruptstatus. this ?eld can be changed by the hc only when in the usbsuspend state. the hc can move from the usbsuspend state to the usbresume state after detecting the resume signaling from a downstream port. the hc enters usbreset after a software reset and a hardware reset. the latter also resets the root hub and asserts subsequent reset signaling to downstream ports. 5 to 0 - reserved table 11: hccontrol register: bit description continued bit symbol description table 12: hccommandstatus register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset 00h access r bit 23 22 21 20 19 18 17 16 symbol reserved soc[1:0] reset 00000000 access rrrrrrrr
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 48 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.1.4 hcinterruptstatus register (r/w: 03h/83h) this register provides the status of the events that cause hardware interrupts. when an event occurs, the hc sets the corresponding bit in this register. when a bit is set, a hardware interrupt is generated if the interrupt is enabled in the hcinterruptenable register (see section 10.1.5 ) and bit masterinterruptenable is set. the hcd can clear individual bits in this register by writing logic 1 to the bit positions to be cleared, but cannot set any of these bits. conversely, the hc can set bits in this register, but cannot clear the bits. code (hex): 03 read code (hex): 83 write bit 15 14 13 12 11 10 9 8 symbol reserved reset 00h access r/w bit 7 6 5 4 3 2 1 0 symbol reserved hcr reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 13: hccommandstatus register: bit description bit symbol description 31 to 18 - reserved 17 to 16 soc[1:0] schedulingoverruncount: the ?eld is incremented on each scheduling overrun error. it is initialized to 00b and wraps around at 11b. it will be incremented when a scheduling overrun is detected even if schedulingoverrun in hcinterruptstatus has already been set. this is used by hcd to monitor any persistent scheduling problems. 15 to 1 - reserved 0 hcr hostcontrollerreset: this bit is set by the hcd to initiate a software reset of the hc. regardless of the functional state of the hc, it moves to the usbsuspend state in which most of the operational registers are reset, except those stated otherwise, and no host bus accesses are allowed. this bit is cleared by the hc upon the completion of the reset operation. the reset operation must be completed within 10 m s. this bit, when set, does not cause a reset to the root hub and no subsequent reset signaling will be asserted to its downstream ports. table 14: hcinterruptstatus register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset 00h access r/w
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 49 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.1.5 hcinterruptenable register (r/w: 04h/84h) each enable bit in the hcinterruptenable register corresponds to an associated interrupt bit in the hcinterruptstatus register. the hcinterruptenable register is used to control which events generate a hardware interrupt. a hardware interrupt is requested on the host bus when three conditions occur: ? a bit is set in the hcinterruptstatus register ? the corresponding bit in the hcinterruptenable register is set ? bit masterinterruptenable is set. bit 23 22 21 20 19 18 17 16 symbol reserved reset 00h access r/w bit 15 14 13 12 11 10 9 8 symbol reserved reset 00h access r/w bit 7 6 5 4 3 2 1 0 symbol reserved rhsc fno ue rd sf reserved so reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 15: hcinterruptstatus register: bit description bit symbol description 31 to 7 - reserved 6 rhsc roothubstatuschange: this bit is set when the content of hcrhstatus or the content of any of hcrhportstatus[1:2] has changed. 5 fno framenumberover?ow: this bit is set when the msb of hcfmnumber (bit 15) changes value. 4ue unrecoverableerror: this bit is set when the hc detects a system error not related to usb. the hc does not proceed with any processing nor signaling before the system error has been corrected. the hcd clears this bit after the hc has been reset. ohci: always set to logic 0. 3rd resumedetected: this bit is set when the hc detects that a device on the usb is asserting resume signaling from a state of no resume signaling. this bit is not set when hcd enters the usbresume state. 2sf startofframe: at the start of each frame, this bit is set by the hc and an sof is generated. 1 - reserved 0so schedulingoverrun: this bit is set when the usb schedules for current frame overruns. a scheduling overrun will also cause the schedulingoverruncount of hccommandstatus to be incremented.
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 50 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. writing a logic 1 to a bit in this register sets the corresponding bit, whereas writing a logic 0 to a bit in this register leaves the corresponding bit unchanged. on a read, the current value of this register is returned. code (hex): 04 read code (hex): 84 write table 16: hcinterruptenable register: bit allocation bit 31 30 29 28 27 26 25 24 symbol mie reserved reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved reset 00h access r/w bit 15 14 13 12 11 10 9 8 symbol reserved reset 00h access r/w bit 7 6 5 4 3 2 1 0 symbol reserved rhsc fno ue rd sf reserved so reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 17: hcinterruptenable register: bit description bit symbol description 31 mie masterinterruptenable by the hcd: a logic 0 is ignored by the hc. a logic 1 enables interrupt generation by events speci?ed in other bits of this register. 30 to 7 - reserved 6 rhsc 0 ignore 1 enable interrupt generation due to root hub status change 5 fno 0 ignore 1 enable interrupt generation due to frame number over?ow 4ue 0 ignore 1 enable interrupt generation due to unrecoverable error 3rd 0 ignore 1 enable interrupt generation due to resume detect 2sf 0 ignore 1 enable interrupt generation due to start of frame 1 - reserved 0so 0 ignore 1 enable interrupt generation due to scheduling overrun
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 51 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.1.6 hcinterruptdisable register (r/w: 05h/85h) each disable bit in the hcinterruptdisable register corresponds to an associated interrupt bit in the hcinterruptstatus register. the hcinterruptdisable register is coupled with the hcinterruptenable register. thus, writing a logic 1 to a bit in this register clears the corresponding bit in the hcinterruptenable register, whereas writing a logic 0 to a bit in this register leaves the corresponding bit in the hcinterruptenable register unchanged. on a read, the current value of the hcinterruptenable register is returned. code (hex): 05 read code (hex): 85 write table 18: hcinterruptdisable register: bit allocation bit 31 30 29 28 27 26 25 24 symbol mie reserved reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved reset 00h access r/w bit 15 14 13 12 11 10 9 8 symbol reserved reset 00h access r/w bit 7 6 5 4 3 2 1 0 symbol reserved rhsc fno ue rd sf reserved so reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 19: hcinterruptdisable register: bit description bit symbol description 31 mie a logic 0 is ignored by the hc. a logic 1 disables interrupt generation due to events speci?ed in other bits of this register. this bit is set after a hardware or software reset. 30 to 7 - reserved 6 rhsc 0 ignore 1 disable interrupt generation due to root hub status change
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 52 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.2 hc frame counter registers 10.2.1 hcfminterval register (r/w: 0dh/8dh) the hcfminterval register contains a 14-bit value which indicates the bit time interval in a frame (that is, between two consecutive sofs), and a 15-bit value indicating the full-speed maximum packet size that the hc may transmit or receive without causing a scheduling overrun. the hcd may carry out minor adjustments on the frameinterval by writing a new value at each sof. this allows the hc to synchronize with an external clock source and to adjust any unknown clock offset. code (hex): 0d read code (hex): 8d write 5 fno 0 ignore 1 disable interrupt generation due to frame number over?ow 4ue 0 ignore 1 disable interrupt generation due to unrecoverable error 3rd 0 ignore 1 disable interrupt generation due to resume detect 2sf 0 ignore 1 disable interrupt generation due to start of frame 1 - reserved 0so 0 ignore 1 disable interrupt generation due to scheduling overrun table 19: hcinterruptdisable register: bit description continued bit symbol description table 20: hcfminterval register: bit allocation bit 31 30 29 28 27 26 25 24 symbol fit fsmps[14:8] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol fsmps[7:0] reset 00h access r/w bit 15 14 13 12 11 10 9 8 symbol reserved fi[13:8] reset 00101110 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol fi[7:0] reset dfh access r/w
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 53 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.2.2 hcfmremaining register (r: 0eh) the hcfmremaining register is a 14-bit down counter showing the bit time remaining in the current frame. code (hex): 0e read table 21: hcfminterval register: bit description bit symbol description 31 fit frameintervaltoggle: the hcd toggles this bit whenever it loads a new value to frameinterval. 30 to 16 fsmps [14:0] fslargestdatapacket (fsmaxpacketsize): speci?es a value which is loaded into the largest data packet counter at the beginning of each frame. the counter value represents the largest amount of data in bits which can be sent or received by the hc in a single transaction at any given time without causing a scheduling overrun. the ?eld value is calculated by the hcd. 15 to 14 - reserved 13 to 0 fi[13:0] frameinterval: speci?es the interval between two consecutive sofs in bit times. the default value is 11999. the hcd must save the current value of this ?eld before resetting the hc. setting the hostcontrollerreset ?eld of the hccommandstatus register will cause the hc to reset this ?eld to its default value. hcd may choose to restore the saved value upon completing the reset sequence. table 22: hcfmremaining register: bit allocation bit 31 30 29 28 27 26 25 24 symbol frt reserved reset 00000000 access rrrrrrrr bit 23 22 21 20 19 18 17 16 symbol reserved reset 00h access r bit 15 14 13 12 11 10 9 8 symbol reserved fr[13:8] reset 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol fr[7:0] reset 00h access r
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 54 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.2.3 hcfmnumber register (r: 0fh) the hcfmnumber register is a 16-bit counter. it provides a timing reference for events happening in the hc and the hcd. the hcd may use the 16-bit value speci?ed in this register and generate a 32-bit frame number without requiring frequent access to the register. code (hex): 0f read table 23: hcfmremaining register: bit description bit symbol description 31 frt frameremainingtoggle: this bit is loaded from the frameintervaltoggle ?eld of the hcfminterval register whenever frameremaining reaches 0. this bit is used by the hcd for synchronization between frameinterval and frameremaining. 30 to 14 - reserved 13 to 0 fr[13:0] frameremaining: this counter is decremented at each bit time. when it reaches zero, it is reset by loading the frameinterval value speci?ed in the hcfminterval register at the next bit time boundary. when entering the usboperational state, the hc reloads it with the content of the frameinterval part of the hcfminterval register and uses the updated value from the next sof. table 24: hcfmnumber register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset 00h access r bit 23 22 21 20 19 18 17 16 symbol reserved reset 00h access r bit 15 14 13 12 11 10 9 8 symbol fn[15:8] reset 00h access r bit 7 6 5 4 3 2 1 0 symbol fn[7:0] reset 00h access r table 25: hcfmnumber register: bit description bit symbol description 31 to 16 - reserved 15 to 0 fn[15:0] framenumber: this ?eld is incremented when hcfmremaining is reloaded. it rolls over to 0000h after ffffh. when the usboperational state is entered, this ?eld will be incremented automatically. the hc will set bit startofframe in the hcinterruptstatus register.
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 55 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.2.4 hclsthreshold register (r/w: 11h/91h) the hclsthreshold register contains an 11-bit value used by the hc to determine whether to commit to the transfer of a maximum of 8-byte ls packet before eof. neither the hc nor the hcd is allowed to change this value. code (hex): 11 read code (hex): 91 write 10.3 hc root hub registers all registers included in this partition are dedicated to the usb root hub, which is an integral part of the hc although it is functionally a separate entity. the host controller driver (hcd) emulates usbd accesses to the root hub via a register interface. the hcd maintains many usb-de?ned hub features that are not required to be supported in hardware. for example, the hubs device, con?guration, interface, endpoint descriptors, as well as some static ?elds of the class descriptor, are maintained only in the hcd. the hcd also maintains and decodes the root hubs device address as well as other minor operations more suited for software than for hardware. the root hub registers were developed to match the bit organization and operation of typical hubs found in the system. table 26: hclsthreshold register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset 00h access r/w bit 23 22 21 20 19 18 17 16 symbol reserved reset 00h access r/w bit 15 14 13 12 11 10 9 8 symbol reserved lst[10:8] reset 00000110 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol lst[7:0] reset 28h access r/w table 27: hclsthreshold register: bit description bit symbol description 31 to 11 - reserved 10 to 0 lst[10:0] lsthreshold: contains a value that is compared to the frameremaining ?eld before a low-speed transaction is initiated. the transaction is started only if frameremaining 3 this ?eld. the value is calculated by the hcd, which considers transmission and set-up overhead. default value: 1576 (628h)
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 56 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. four 32-bit registers have been de?ned: ? hcrhdescriptora ? hcrhdescriptorb ? hcrhstatus ? hcrhportstatus[1:ndp] each register is read and written as a dword. these registers are only written during initialization to correspond with the system implementation. the hcrhdescriptora and hcrhdescriptorb registers are writeable regardless of the hcs usb states. hcrhstatus and hcrhportstatus are writeable during the usboperational state only. 10.3.1 hcrhdescriptora register (r/w: 12h/92h) the hcrhdescriptora register is the ?rst register of two describing the characteristics of the root hub. reset values are implementation-speci?c (is). the descriptor length (11), descriptor type and hub controller current (0) ?elds of the hub class descriptor are emulated by the hcd. all other ?elds are located in registers hcrhdescriptora and hcrhdescriptorb. remark: is denotes an implementation-speci?c reset value for that ?eld. code (hex): 12 read code (hex): 92 write table 28: hcrhdescriptora register: bit description bit 31 30 29 28 27 26 25 24 symbol potpgt[7:0] reset is access r/w bit 23 22 21 20 19 18 17 16 symbol reserved reset 00h access r/w bit 15 14 13 12 11 10 9 8 symbol reserved nocp ocpm dt nps psm reset 0 0 0 is is 0 is is access r r r r/w r/w r r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved ndp[1:0] reset 000000isis access rrrrrrrr
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 57 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. table 29: hcrhdescriptora register: bit description bit symbol description 31 to 24 potpgt [7:0] powerontopowergoodtime: this byte speci?es the duration hcd has to wait before accessing a powered-on port of the root hub. the unit of time is 2 ms. the duration is calculated as potpgt 2ms. 23 to 13 - reserved 12 nocp noovercurrentprotection: this bit describes how the overcurrent status for the root hub ports are reported. when this bit is cleared, the overcurrentprotectionmode ?eld speci?es global or per-port reporting. 0 overcurrent status is reported collectively for all downstream ports 1 no overcurrent reporting supported 11 ocpm overcurrentprotectionmode: this bit describes how the overcurrent status for the root hub ports is reported. at reset, this ?eld re?ects the same mode as powerswitchingmode. this ?eld is valid only if the noovercurrentprotection ?eld is cleared. 0 overcurrent status is reported collectively for all downstream ports. 1 overcurrent status is reported on a per-port basis. on power-up, clear this bit and then set it to logic 1. 10 dt devicetype: this bit speci?es that the root hub is not a compound deviceit is not permitted. this ?eld will always read/write 0. 9 nps nopowerswitching: this bit is used to specify whether power switching is supported or ports are always powered. it is implementation-speci?c. when this bit is cleared, the bit powerswitchingmode speci?es global or per-port switching. 0 ports are power switched 1 ports are always powered on when the hc is powered on 8 psm powerswitchingmode: this bit is used to specify how the power switching of the root hub ports is controlled. it is implementation-speci?c. this ?eld is valid only if the nopowerswitching ?eld is cleared. 0 all ports are powered at the same time 1 each port is powered individually. this mode allows port power to be controlled by either the global switch or per-port switching. if bit portpowercontrolmask is set, the port responds to only port power commands (set/clearportpower). if the port mask is cleared, then the port is controlled only by the global power switch (set/clearglobalpower). 7 to 2 - reserved 1 to 0 ndp[1:0] numberdownstreamports: these bits specify the number of downstream ports supported by the root hub. the maximum number of ports supported by the isp1161a1 is 2.
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 58 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.3.2 hcrhdescriptorb register (r/w: 13h/93h) the hcrhdescriptorb register is the second register of two describing the characteristics of the root hub. these ?elds are written during initialization to correspond with the system implementation. reset values are implementation-speci?c (is). code (hex): 13 read code (hex): 93 write table 30: hcrhdescriptorb register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset n/a access r bit 23 22 21 20 19 18 17 16 symbol reserved ppcm[2:0] reset n/a n/a n/a n/a n/a is is is access rrrrrr/wr/wr/w bit 15 14 13 12 11 10 9 8 symbol reserved reset n/a access r bit 7 6 5 4 3 2 1 0 symbol reserved dr[2:0] reset n/a n/a n/a n/a n/a is is is access rrrrrr/wr/wr/w
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 59 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.3.3 hcrhstatus register (r/w: 14h/94h) the hcrhstatus register is divided into two parts. the lower word of a dword represents the hub status ?eld and the upper word represents the hub status change ?eld. reserved bits should always be written as logic 0. code (hex): 14 read code (hex): 94 write table 31: hcrhdescriptorb register: bit description bit symbol description 31 to 19 - reserved 18 to 16 ppcm[2:0] portpowercontrolmask: each bit indicates whether a port is affected by a global power control command when powerswitchingmode is set. when set, the ports power state is only affected by per-port power control (set/clearportpower). when cleared, the port is controlled by the global power switch (set/clearglobalpower). if the device is con?gured to global switching mode (powerswitchingmode = 0), this ?eld is not valid. bit 0 reserved bit 1 ganged-power mask on port #1 bit 2 ganged-power mask on port #2 15 to 3 - reserved 2 to 0 dr[2:0] deviceremovable: each bit is dedicated to a port of the root hub. when cleared, the attached device is removable. when set, the attached device is not removable. bit 0 reserved bit 1 device attached to port #1 bit 2 device attached to port #2 table 32: hcrhstatus register: bit allocation bit 31 30 29 28 27 26 25 24 symbol crwe reserved reset 00000000 access wrrrrrrr bit 23 22 21 20 19 18 17 16 symbol reserved ocic lpsc reset 00000000 access rrrrrrr/wr/w bit 15 14 13 12 11 10 9 8 symbol drwe reserved reset 00000000 access r/wrrrrrrr
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 60 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. bit 7 6 5 4 3 2 1 0 symbol reserved oci lps reset 00000000 access rrrrrrrr/w table 33: hcrhstatus register: bit description bit symbol description 31 crwe on write clearremotewakeupenable: writing a logic 1 clears deviceremovewakeupenable. writing a logic 0 has no effect. 30 to 18 - reserved 17 ocic overcurrentindicatorchange: this bit is set by hardware when a change has occurred to the oci ?eld of this register. the hcd clears this bit by writing a logic 1. writing a logic 0 has no effect. 16 lpsc on read localpowerstatuschange: the root hub does not support the local power status feature. therefore, this bit is always read as logic 0. on write setglobalpower: in global power mode (powerswitchingmode=0), this bit is written to logic 1 to turn on power to all ports (clear portpowerstatus). in per-port power mode, it sets portpowerstatus only on ports whose bit portpowercontrolmask is not set. writing a logic 0 has no effect. 15 drwe on read deviceremotewakeupenable: this bit enables the bit connectstatuschange as a resume event, causing a state transition usbsuspend to usbresume and setting the resumedetected interrupt. 0 connectstatuschange is not a remote wake-up event 1 connectstatuschange is a remote wake-up event on write setremotewakeupenable: writing a logic 1 sets deviceremovewakeupenable. writing a logic 0 has no effect. 14 to 2 - reserved 1 oci overcurrentindicator: this bit reports overcurrent conditions when global reporting is implemented. when set, an overcurrent condition exists. when clear, all power operations are normal. if per-port overcurrent protection is implemented this bit is always logic 0. 0 lps on read localpowerstatus: the root hub does not support the local power status feature. therefore, this bit is always read as logic 0. on write clearglobalpower: in global power mode (powerswitchingmode = 0), this bit is written to logic 1 to turn off power to all ports (clear portpowerstatus). in per-port power mode, it clears portpowerstatus only on ports whose bit portpowercontrolmask is not set. writing a logic 0 has no effect.
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 61 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.3.4 hcrhportstatus[1:2] register (r/w [1]:15h/95h, [2]: 16h/96h) the hcrhportstatus[1:2] register is used to control and report port events on a per-port basis. numberdownstreamports represents the number of hcrhportstatus registers that are implemented in hardware. the lower word is used to re?ect the port status, whereas the upper word re?ects the status change bits. some status bits are implemented with special write behavior. if a transaction (token through handshake) is in progress when a write to change port status occurs, the resulting port status change must be postponed until the transaction completes. reserved bits should always be written logic 0. code (hex): [1] = 15, [2] = 16 read code (hex): [1] = 95, [2] = 96 write table 34: hcrhportstatus[1:2] register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset 00h access r/w bit 23 22 21 20 19 18 17 16 symbol reserved prsc ocic pssc pesc csc reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved lsda pps reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved prs poci pss pes ccs reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 35: hcrhportstatus[1:2] register: bit description bit symbol description 31 to 21 - reserved 20 prsc portresetstatuschange: this bit is set at the end of the 10 ms port reset signal. the hcd writes a logic 1 to clear this bit. writing a logic 0 has no effect. 0 port reset is not complete 1 port reset is complete 19 ocic portovercurrentindicatorchange: this bit is valid only if overcurrent conditions are reported on a per-port basis. this bit is set when root hub changes the portovercurrentindicator bit. the hcd writes a logic 1 to clear this bit. writing a logic 0 has no effect. 0 no change in portovercurrentindicator 1 portovercurrentindicator has changed
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 62 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 18 pssc portsuspendstatuschange: this bit is set when the full resume sequence has been completed. this sequence includes the 20 s resume pulse, ls eop, and 3 ms resynchronization delay. the hcd writes a logic 1 to clear this bit. writing a logic 0 has no effect. this bit is also cleared when resetstatuschange is set. 0 resume is not complete 1 resume is complete 17 pesc portenablestatuschange: this bit is set when hardware events cause bit portenablestatus to be cleared. changes from hcd writes do not set this bit. the hcd writes a logic 1 to clear this bit. writing a logic 0 has no effect. 0 no change in portenablestatus 1 change in portenablestatus 16 csc connectstatuschange: this bit is set whenever a connect or disconnect event occurs. the hcd writes a logic 1 to clear this bit. writing a logic 0 has no effect. if currentconnectstatus is cleared when a setportreset, setportenable, or setportsuspend write occurs, this bit is set to force the driver to reevaluate the connection status since these writes should not occur if the port is disconnected. 0 no change in currentconnectstatus 1 change in currentconnectstatus remark: if bit deviceremovable[ndp] is set, this bit is set only after a root hub reset to inform the system that the device is connected. 15 to 10 - reserved 9 lsda (read) lowspeeddeviceattached: this bit indicates the speed of the device connected to this port. when set, a low-speed device is connected to this port. when clear, a full-speed device is connected to this port. this ?eld is valid only when the currentconnectstatus is set. 0 full-speed device attached 1 low-speed device attached (write) clearportpower: the hcd clears bit portpowerstatus by writing a logic 1 to this bit. writing a logic 0 has no effect. table 35: hcrhportstatus[1:2] register: bit description continued bit symbol description
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 63 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8 pps (read) portpowerstatus: this bit re?ects the port power status, regardless of the type of power switching implemented. this bit is cleared if an overcurrent condition is detected. the hcd sets this bit by writing setportpower or setglobalpower. the hcd clears this bit by writing clearportpower or clearglobalpower. which power control switches are enabled is determined by powerswitchingmode. in the global switching mode (powerswitchingmode = 0), only set/clearglobalpower controls this bit. in per-port power switching (powerswitchingmode = 1), if bit portpowercontrolmask[ndp] for the port is set, only set/clearportpower commands are enabled. if the mask is not set, only set/clearglobalpower commands are enabled. when port power is disabled, currentconnectstatus, portenablestatus, portsuspendstatus, and portresetstatus should be reset. 0 port power is off 1 port power is on (write) setportpower: the hcd writes a logic 1 to set bit portpowerstatus. writing a logic 0 has no effect. remark: this bit always reads logic 1 if power switching is not supported. 7 to 5 - reserved 4 prs (read) portresetstatus: when this bit is set by a write to setportreset, port reset signaling is asserted. when reset is completed, this bit is cleared when portresetstatuschange is set. this bit cannot be set if currentconnectstatus is cleared. 0 port reset signal is not active 1 port reset signal is active (write) setportreset: the hcd sets the port reset signaling by writing a logic 1 to this bit. writing a logic 0 has no effect. if currentconnectstatus is cleared, this write does not set portresetstatus but instead sets connectstatuschange. this informs the driver that it attempted to reset a disconnected port. 3 poci (read) portovercurrentindicator: this bit is valid only when the root hub is con?gured in such a way that overcurrent conditions are reported on a per-port basis. if per-port overcurrent reporting is not supported, this bit is set to logic 0. if cleared, all power operations are normal for this port. if set, an overcurrent condition exists on this port. this bit always re?ects the overcurrent input signal. 0 no overcurrent condition 1 overcurrent condition detected (write) clearsuspendstatus: the hcd writes a logic 1 to initiate a resume. writing a logic 0 has no effect. a resume is initiated only if portsuspendstatus is set. table 35: hcrhportstatus[1:2] register: bit description continued bit symbol description
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 64 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 2 pss (read) portsuspendstatus: this bit indicates whether the port is suspended or in the resume sequence. it is set by a setsuspendstate write and cleared when portsuspendstatuschange is set at the end of the resume interval. this bit cannot be set if currentconnectstatus is cleared. this bit is also cleared when portresetstatuschange is set at the end of the port reset or when the hc is placed in the usbresume state. if an upstream resume is in progress, it is propagated to the hc. 0 port is not suspended 1 port is suspended (write) setportsuspend: the hcd sets bit portsuspendstatus by writing a logic 1 to this bit. writing a logic 0 has no effect. if currentconnectstatus is cleared, this write action does not set portsuspendstatus; instead it sets connectstatuschange. this informs the driver that it attempted to suspend a disconnected port. 1 pes (read) portenablestatus: this bit indicates whether the port is enabled or disabled. the root hub can clear this bit when an overcurrent condition, disconnect event, switched-off power, or operational bus error such as babble is detected. this change also causes portenablestatuschange to be set. the hcd sets this bit by writing setportenable and clears it by writing clearportenable. this bit cannot be set when currentconnectstatus is cleared. this bit is also set at the completion of a port reset when resetstatuschange is set or port is suspended when suspendstatuschange is set. 0 port is disabled 1 port is enabled (write) setportenable: the hcd sets portenablestatus by writing a logic 1. writing a logic 0 has no effect. if currentconnectstatus is cleared, this write does not set portenablestatus, but instead sets connectstatuschange. this informs the driver that it attempted to enable a disconnected port. 0 ccs (read) currentconnectstatus: this bit re?ects the current state of the downstream port. 0 no device connected 1 device connected (write) clearportenable: the hcd writes a logic 1 to this bit to clear bit portenablestatus. writing a logic 0 has no effect. currentconnectstatus is not affected by any write. remark: this bit always reads logic 1 when the attached device is nonremovable (deviceremovable[ndp]). table 35: hcrhportstatus[1:2] register: bit description continued bit symbol description
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 65 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.4 hc dma and interrupt control registers 10.4.1 hchardwarecon?guration register (r/w: 20h/a0h) 1. bit 0, interruptpinenable, is used as pin int1s master interrupt enable. this bit should be used together with register hc m pinterruptenable to enable pin int1. 2. bits 4 and 3, databuswidth[1:0], are ?xed at logic 0 and logic 1 for the isp1161a1. code (hex): 20 read code (hex): a0 write table 36: hchardwarecon?guration register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved 2_down stream port15k resistorsel suspend clknotstop analogoc enable reserved dackmode reset 00000 000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol eotinput polarity dackinput polarity dreq output polarity databuswidth[1:0] interrupt output polarity interrupt pintrigger interruptpin enable reset 00101 000 access r/w r/w r/w r/w r/w r/w r/w r/w table 37: hchardwarecon?guration register: bit description bit symbol description 15 to 13 - reserved 12 2_downstreamport15k resistorsel 0 use external 15 k w resistors for downstream ports 1 built-in resistors for downstream ports 11 suspendclknotstop 0 clock can be stopped 1 clock can not be stopped 10 analogocenable 0 use external oc detection. digital input 1 use on-chip oc detection. analog input 9 - reserved 8 dackmode 0 normal operation. d a ck1 is used with read and write signals 1 reserved 7 eotinputpolarity 0 active low 1 active high 6 dackinputpolarity 0 active low 1 reserved
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 66 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.4.2 hcdmacon?guration register (r/w: 21h/a1h) code (hex): 21 read code (hex): a1 write 5 dreqoutputpolarity 0 active low 1 active high 4 to 3 databuswidth[1:0] 01 16 bits others reserved 2 interruptoutputpolarity 0 active low 1 active high 1 interruptpintrigger 0 interrupt is level-triggered 1 interrupt is edge-triggered 0 interruptpinenable 0 int1 is disabled 1 pin int1 is enabled table 37: hchardwarecon?guration register: bit description continued bit symbol description table 38: hcdmacon?guration register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved reset 00h access r/w bit 7 6 5 4 3 2 1 0 symbol reserved burstlen[1:0] dma enable reserved dma counter select itl_atl_ dataselect dmaread writeselect reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 39: hcdmacon?guration register: bit description bit symbol description 15 to 7 - reserved 6 to 5 burstlen[1:0] 00 single-cycle burst dma 01 4-cycle burst dma 10 8-cycle burst dma 11 reserved 4 dmaenable 0 dma is terminated 1 dma is enabled. this bit will be reset to zero when dma transfer is completed. 3 - reserved
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 67 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.4.3 hctransfercounter register (r/w: 22h/a2h) this register holds the number of bytes of a pio or dma transfer. for a pio transfer, the number of bytes being read or written to the isochronous transfer list (itl) or acknowledged transfer list (atl) buffer ram must be written into this register. for a dma transfer, the number of bytes must be written into this register as well. however, for this counter to be read into the dma counter, the hcd must set bit 2 (dmacounterselect) of the hcdmacon?guration register. the counter value for atl must not be greater than 1000h, and for itl it must not be greater than 800h. when the byte count of the data transfer reaches this value, the hc will generate an internal eot signal to set bit 2 (alleotinterrupt) of the hc m pinterrupt register, and also update the hcbufferstatus register. code (hex): 22 read code (hex): a2 write 2 dmacounter select 0 dma counter not used. external eot must be used 1 enables the dma counter for dma transfer. hctransfercounter register must be ?lled with non-zero values for dreq1 to be raised after bit dma enable is set 1 itl_atl_ dataselect 0 itl buffer ram selected for itl data 1 atl buffer ram selected for atl data 0 dmaread writeselect 0 read from the hc fifo buffer ram 1 write to the hc fifo buffer ram table 39: hcdmacon?guration register: bit description continued bit symbol description table 40: hctransfercounter register: bit allocation bit 15 14 13 12 11 10 9 8 symbol counter value reset 00h access r/w bit 7 6 5 4 3 2 1 0 symbol counter value reset 00h access r/w table 41: hctransfercounter register: bit description bit symbol description 15 to 0 counter value the number of data bytes to be read to or written from ram.
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 68 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.4.4 hc m pinterrupt register (r/w: 24h/a4h) all the bits in this register will be active on power-on reset. however, none of the active bits will cause an interrupt on the interrupt pin (int1) unless they are set by the respective bits in the hc m pinterruptenable register, and together with bit 0 of the hchardwarecon?guration register. after this register (24h for read) is read, the bits that are active will not be reset, until logic 1 is written to the bits in this register (a4h for write) to clear it. to clear all the enabled bits in this register, the hcd must write ffh to this register. code (hex): 24 read code (hex): a4 write table 42: hc m pinterrupt register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved reset 00h access r/w bit 7 6 5 4 3 2 1 0 symbol reserved clkready hc suspended opr_reg reserved alleot interrupt atlint sofitlint reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 43: hc m pinterrupt register: bit description bit symbol description 15 to 7 - reserved 6 clkready 0 no event 1 clock is ready. after a wake-up is sent, there is a wait for clock ready. (maximum is 1 ms, and typical is 160 m s) 5hc suspended 0 no event 1 the hc has been suspended and no usb activity is sent from the microprocessor for each ms. when the microprocessor wants to suspend the hc, the microprocessor must write to the hccontrol register. and when all downstream devices are suspended, then the hc stops sending sof; the hc is suspended by having the hccontrol register written into. 4 opr_reg 0 no event 1 there are interrupts from hc side. need to read hccontrol and hcinterrupt registers to detect type of interrupt on the hc (if the hc requires the operational register to be updated) 3 - reserved 2 alleot interrupt 0 no event 1 implies that data transfer has been completed via pio transfer or dma transfer. occurrence of internal or external eot will set this bit.
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 69 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.4.5 hc m pinterruptenable register (r/w: 25h/a5h) the bits 6:0 in this register are the same as those in the hc m pinterrupt register. they are used together with bit 0 of the hchardwarecon?guration register to enable or disable the bits in the hc m pinterrupt register. at power-on, all bits in this register are masked with logic 0. this means no interrupt request output on the interrupt pin int1 can be generated. when the bit is set to logic 1, the interrupt for the bit is not masked but enabled. code (hex): 25 read code (hex): a5 write 1 atlint 0 no event 1 implies that the microprocessor must read atl data from the hc. this requires that the hcbufferstatus register must ?rst be read. the time for this interrupt depends on the number of clocks bit set for usb activities in each ms. 0 sofitlint 0 no event 1 implies that sof indicates the 1 ms mark. the itl buffer that the hc has handled must be read. to know the itl buffer status, the hcbufferstatus register must ?rst be read. this is for the microprocessor to get iso data to or from the hc. for more information, see the 6th paragraph in section 9.5 . table 43: hc m pinterrupt register: bit description continued bit symbol description table 44: hc m pinterruptenable register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved reset 00h access r/w bit 7 6 5 4 3 2 1 0 symbol reserved clkready hc suspended enable opr interrupt enable reserved eot interrupt enable at l interrupt enable sof interrupt enable reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 45: hc m pinterruptenable register: bit description bit symbol description 15 to 7 - reserved 6 clkready 0 power-up value 1 enables clkready interrupt
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 70 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.5 hc miscellaneous registers 10.5.1 hcchipid register (r: 27h) read this register to get the id of the isp1161a1 silicon chip. the higher byte stands for the product name (here 61h stands for the isp1161a1). the lower byte indicates the revision number of the product including engineering samples. code (hex): 27 read 5hc suspended enable 0 power-up value 1 enables hc suspended interrupt. when the microprocessor wants to suspend the hc, the microprocessor must write to the hccontrol register. and when all downstream devices are suspended, then the hc stops sending sof; the hc is suspended by having the hccontrol register written into. 4 opr interrupt enable 0 power-up value 1 enables the 32-bit operational registers interrupt (if the hc requires the operational register to be updated) 3 - reserved 2eot interrupt enable 0 power-up value 1 enables the eot interrupt which indicates an end of a read/write transfer 1atl interrupt enable 0 power-up value 1 enables atl interrupt. the time for this interrupt depends on the number of clock bits set for usb activities in each ms. 0 sof interrupt enable 0 power-up value 1 enables the interrupt bit due to sof (for the microprocessor dma to get iso data from the hc by ?rst accessing the hcdmacon?guration register) table 45: hc m pinterruptenable register: bit description continued bit symbol description table 46: hcchipid register: bit allocation bit 15 14 13 12 11 10 9 8 symbol chipid[15:8] reset 61h access r bit 7 6 5 4 3 2 1 0 symbol chipid[7:0] reset 23h access r table 47: hcchipid register: bit description bit symbol description 15 to 0 chipid[15:0] isp1161a1s chip id
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 71 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.5.2 hcscratch register (r/w: 28h/a8h) this register is for the hcd to save and restore values when required. code (hex): 28 read code (hex): a8 write 10.5.3 hcsoftwarereset register (w: a9h) this register provides a means for software reset of the hc. to reset the hc, the hcd must write a reset value of f6h to this register. upon receiving the reset value, the hc resets all the registers except its buffer memory. code (hex): a9 write table 48: hcscratch register: bit allocation bit 15 14 13 12 11 10 9 8 symbol scratch[15:8] reset 00h access r/w bit 7 6 5 4 3 2 1 0 symbol scratch[7:0] reset 00h access r/w table 49: hcscratch register: bit description bit symbol description 15 to 0 scratch[15:0] scratch register value table 50: hcsoftwarereset register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reset[15:8] reset 00h access w bit 7 6 5 4 3 2 1 0 symbol reset[7:0] reset 00h access w table 51: hcsoftwarereset register: bit description bit symbol description 15 to 0 reset[15:0] writing a reset value of f6h will cause the hc to reset all the registers except its buffer memory.
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 72 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.6 hc buffer ram control registers 10.6.1 hcitlbufferlength register (r/w: 2ah/aah) write to this register to assign the itl buffer size in bytes: itl0 and itl1 are assigned the same value. for example, if hcitlbufferlength register is set to 2 kbytes, then itl0 and itl1 would be allocated 2 kbytes each. must follow the formula: atl buffer length + 2 (itl buffer size) 1000h (that is, 4 kbytes) where: itl buffer size = itl0 buffer length = itl1 buffer length code (hex): 2a read code (hex): aa write 10.6.2 hcatlbufferlength register (r/w: 2bh/abh) write to this register to assign atl buffer size. code (hex): 2b read code (hex): ab write remark: the maximum total ram size is 1000h (4096 in decimal) bytes. that means itl0 (length) + itl1 (length) + atl (length) 1000h bytes. for example, if atl buffer length has been set to be 800h, then the maximum itl buffer length can only be set as 400h. table 52: hcitlbufferlength register: bit allocation bit 15 14 13 12 11 10 9 8 symbol itlbufferlength[15:8] reset 00h access r/w bit 7 6 5 4 3 2 1 0 symbol itlbufferlength[7:0] reset 00h access r/w table 53: hcitlbufferlength register: bit description bit symbol description 15 to 0 itlbufferlength[15:0] assign itl buffer length table 54: hcatlbufferlength register: bit allocation bit 15 14 13 12 11 10 9 8 symbol atlbufferlength[15:8] reset 00h access r/w
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 73 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.6.3 hcbufferstatus register (r: 2ch) code (hex): 2c read bit 7 6 5 4 3 2 1 0 symbol atlbufferlength[7:0] reset 00h access r/w table 55: hcatlbufferlength register: bit description bit symbol description 15 to 0 atlbufferlength[15:0] assign atl buffer length table 56: hcbufferstatus register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved reset 00h access r bit 7 6 5 4 3 2 1 0 symbol reserved atlbuffer done itl1buffer done itl0buffer done atlbuffer full itl1buffer full itl0buffer full reset 00000000 access rrrrrrrr table 57: hcbufferstatus register: bit description bit symbol description 15 to 6 - reserved 5 atlbuffer done 0 atl buffer not read by hc yet 1 atl buffer read by hc 4 itl1buffer done 0 itl1 buffer not read by hc yet 1 itl1 buffer read by hc 3 itl0buffer done 0 1tl0 buffer not read by hc yet 1 1tl0 buffer read by hc 2 atlbuffer full 0 atl buffer is empty 1 atl buffer is full 1 itl1buffer full 0 1tl1 buffer is empty 1 1tl1 buffer is full 0 itl0buffer full 0 itl0 buffer is empty 1 itl0 buffer is full
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 74 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.6.4 hcreadbackitl0length register (r: 2dh) this registers value stands for the current number of data bytes inside an itl0 buffer to be read back by the microprocessor. the hcd must set the hctransfercounter equivalent to this value before reading back the itl0 buffer ram. code (hex): 2d read 10.6.5 hcreadbackitl1length register (r: 2eh) this registers value stands for the current number of data bytes inside the itl1 buffer to be read back by the microprocessor. the hcd must set the hctransfercounter equivalent to this value before reading back the itl1 buffer ram. code (hex): 2e read table 58: hcreadbackitl0length register: bit allocation bit 15 14 13 12 11 10 9 8 symbol rditl0bufferlength[15:8] reset 00h access r bit 7 6 5 4 3 2 1 0 symbol rditl0bufferlength[7:0] reset 00h access r table 59: hcreadbackitl0length register: bit description bit symbol description 15 to 0 rditl0bufferlength[15:0] the number of bytes for itl0 data to be read back by the microprocessor table 60: hcreadbackitl1length register: bit allocation bit 15 14 13 12 11 10 9 8 symbol rditl1bufferlength[15:8] reset 00h access r bit 7 6 5 4 3 2 1 0 symbol rditl1bufferlength[7:0] reset 00h access r table 61: hcreadbackitl1length register: bit description bit symbol description 15 to 0 rditl1bufferlength[15:0] the number of bytes for itl1 data to be read back by the microprocessor.
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 75 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.6.6 hcitlbufferport register (r/w: 40h/c0h) this is the itl buffer ram read/write port. the bits 15 to 8 contain the data byte that comes from the itl buffer rams even address. the bits 7 to 0 contain the data byte that comes from the itl buffer rams odd address. code (hex): 40 read code (hex): c0 write the hcd must set the byte count into the hctransfercounter register and check the hcbufferstatus register before reading from or writing to the buffer. the hcd must write the command (40h to read, c0h to write) once only, and then read or write both bytes of the data word. after every read/write, the pointer of itl buffer ram will be automatically increased by two to point to the next data word until it reaches the value of the hctransfercounter register; otherwise, an internal eot signal is not generated to set bit 2 (alleotinterrupt) of the hc m pinterrupt register and update the hcbufferstatus register. the hcd must take care of the fact that the internal buffer ram is organized in bytes. the hcd must write the byte count into the hctransfercounter register, but the hcd reads or writes the buffer ram by 16 bits (by 1 data word). 10.6.7 hcatlbufferport register (r/w: 41h/c1h) this is the atl buffer ram read/write port. bits 15 to 8 contain the data byte that comes from the acknowledged transfer list (atl) buffer rams odd address. bits 7 to 0 contain the data byte that comes from the atl buffer rams even address. code (hex): 41 read code (hex): c1 write table 62: hcitlbufferport register: bit allocation bit 15 14 13 12 11 10 9 8 symbol dataword[15:8] reset 00h access r/w bit 7 6 5 4 3 2 1 0 symbol dataword[7:0] reset 00h access r/w table 63: hcitlbufferport register: bit description bit symbol description 15 to 0 dataword[15:0] read/write itl buffer rams two data bytes. table 64: hcatlbufferport register: bit allocation bit 15 14 13 12 11 10 9 8 symbol dataword[15:8] reset 00h access r/w
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 76 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. the hcd must set the byte count into the hctransfercounter register and check the hcbufferstatus register before reading from or writing to the buffer. the hcd must write the command (41h to read, c1h to write) once only, and then read or write both bytes of the data word. after every read/write, the pointer of atl buffer ram will be automatically increased by two to point to the next data word until it reaches the value of the hctransfercounter register; otherwise, an internal eot signal is not generated to set the bit 2 (alleotinterrupt) of the hc m pinterrupt register and update the hcbufferstatus register. the hcd must take care of the difference: the internal buffer ram is organized in bytes, so the hcd must write the byte count into the hctransfercounter register, but the hcd reads or writes the buffer ram by 16 bits (by 1 data word). bit 7 6 5 4 3 2 1 0 symbol dataword[7:0] reset 00h access r/w table 65: hcatlbufferport register: bit description bit symbol description 15 to 0 dataword[15:0] read/write atl buffer rams two data bytes.
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 77 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 11. usb device controller (dc) the device controller (dc) in the isp1161a1 is based on the philips isp1181b usb full-speed interface device ic. the functionality, commands, and register sets are the same as isp1181b in 16-bit bus mode. if there is any difference between the isp1181b and isp1161a1 data sheets, in terms of the dc functionality, the isp1161a1 data sheet supersedes content in the isp1181b data sheet. in general the dc in an isp1161a1 provides 16 endpoints for usb device implementation. each endpoint can be allocated an amount of ram space in the on-chip ping-pong buffer ram. remark: the ping-pong buffer ram for the dc is independent of the buffer ram in the hc. when the buffer ram is full, the dc will transfer the data in the buffer ram to the usb bus. when the buffer ram is empty, an interrupt is generated to notify the microprocessor to feed in the data. the transfer of data between the microprocessor and the dc can be done in programmed i/o (pio) mode or in dma mode. 11.1 dc data transfer operation the following session explains how the dc of an isp1161a1 handles an in data transfer and an out data transfer. in the device mode, the isp1161a1 acts as a usb device: an in data transfer means transfer from the isp1161a1 to an external usb host (through the upstream port) and an out transfer means transfer from external usb host to the isp1161a1. 11.1.1 in data transfer ? the arrival of the in token is detected by the sie by decoding the pid. ? the sie also checks for the device number and endpoint number and veri?es whether they are acceptable. ? if the endpoint is enabled, the sie checks the contents of the dcendpointstatus register. if the endpoint is full, the contents of the fifo are sent during the data phase, otherwise a not acknowledge (nak) handshake is sent. ? after the data phase, the sie expects a handshake (ack) from the host (except for iso endpoints). ? on receiving the handshake (ack), the sie updates the contents of the dcendpointstatus register and the dcinterrupt register, which in turn generates an interrupt to the microprocessor. for iso endpoints, the dcinterrupt register is updated as soon as data is sent because there is no handshake phase. ? on receiving an interrupt, the microprocessor reads the dcinterrupt register. it will know which endpoint has generated the interrupt and reads the contents of the corresponding dcendpointstatus register. if the buffer is empty, it ?lls up the buffer, so that data can be sent by the sie at the next in token phase. 11.1.2 out data transfer ? the arrival of the out token is detected by the sie by decoding the pid.
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 78 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. ? the sie also checks for the device number and endpoint number and veri?es whether they are acceptable. ? if the endpoint is enabled, the sie checks the contents of the dcendpointstatus register. if the endpoint is empty, the data from usb is stored to fifo during the data phase, otherwise a nak handshake is sent. ? after the data phase, the sie sends a handshake (ack) to the host (except for iso endpoints). ? the sie updates the contents of the dcendpointstatus register and the dcinterrupt register, which in turn generates an interrupt to the microprocessor. for iso endpoints, the dcinterrupt register is updated as soon as data is received because there is no handshake phase. ? on receiving interrupt, the microprocessor reads the dcinterrupt register. it will know which endpoint has generated the interrupt and reads the content of the corresponding dcendpointstatus register. if the buffer is full, it empties the buffer, so that data can be received by the sie at the next out token phase. 11.2 device dma transfer 11.2.1 dma for in endpoint (internal dc to external usb host) when the internal dma handler is enabled and at least one buffer (ping or pong) is free, the dreq2 line is asserted. the external dma controller then starts negotiating for control of the bus. as soon as it has access, it asserts the d a ck2 line and starts writing data. the burst length is programmable. when the number of bytes equal to the burst length has been written, the dreq2 line is de-asserted. as a result, the dma controller de-asserts the d a ck2 line and releases the bus. at that moment the whole cycle restarts for the next burst. when the buffer is full, the dreq2 line will be de-asserted and the buffer is validated (which means that it will be sent to the host when the next in token comes in). when the dma transfer is terminated, the buffer is also validated (even if it is not full). a dma transfer is terminated when any of the following conditions are met: ? the dma count is complete ? bit dmaen = 0 ? the dma controller asserts eot. 11.2.2 dma for out endpoint (external usb host to internal dc) when the internal dma handler is enabled and at least one buffer is full, the dreq2 line is asserted. the external dma controller then starts negotiating for control of the bus, and as soon as it has access, it asserts the d a ck2 line and starts reading the data. the burst length is programmable. when the number of bytes equal to the burst length has been read, the dreq2 line is de-asserted. as a result, the dma controller de-asserts the d a ck2 line and releases the bus. at that moment the whole cycle restarts for the next burst. when all data are read, the dreq2 line will be de-asserted and the buffer is cleared (which means that it can be overwritten when a new packet comes in).
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 79 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. a dma transfer is terminated when any of the following conditions are met: ? the dma count is complete ? dmaen = 0 ? the dma controller asserts eot. when the dma transfer is terminated, the buffer is also cleared (even if the data is not completely read) and the dma handler is disabled automatically. for the next dma transfer, the dma controller as well as the dma handler must be re-enabled. 11.3 endpoint descriptions 11.3.1 endpoints with programmable fifo size each usb device is logically composed of several independent endpoints. an endpoint acts as a terminus of a communication ?ow between the host and the device. at design time each endpoint is assigned a unique number (endpoint identi?er, see ta b l e 6 6 ). the combination of the device address (given by the host during enumeration), the endpoint number and the transfer direction allows each endpoint to be uniquely referenced. the dc has 16 endpoints: endpoint 0 (control in and out) plus 14 con?gurable endpoints, which can be individually de?ned as interrupt/bulk/isochronous, in or out. each enabled endpoint has an associated fifo, which can be accessed either via the programmed i/o interface or via dma. 11.3.2 endpoint access ta b l e 6 6 lists the endpoint access modes and programmability. all endpoints support i/o mode access. endpoints 1 to 14 also support dma access. dc fifo dma access is selected and enabled via bits epidx[3:0] and dmaen of the dcdmacon?guration register. a detailed description of the dc dma operation is given in section 12 . [1] the total amount of fifo storage allocated to enabled endpoints must not exceed 2462 bytes. [2] the data ?ow direction is determined by bit epdir in the dcendpointcon?guration register; see section 13.1.1 . in: input for the usb host (isp1161a1 transmits); out: output from the usb host (isp1161a1 receives). 11.3.3 endpoint fifo size the size of the fifo determines the maximum packet size that the hardware can support for a given endpoint. only enabled endpoints are allocated space in the shared fifo storage, disabled endpoints have zero bytes. ta b l e 6 7 lists the programmable fifo sizes. the following bits in the endpoint con?guration register (ecr) affect fifo allocation: ? endpoint enable bit (fifoen) table 66: endpoint access and programmability endpoint identi?er fifo size [1] (bytes) double buffering i/o mode access dma mode access endpoint type 0 64 (?xed) no yes no control out [2] 0 64 (?xed) no yes no control in [2] 1 to 14 programmable supported supported supported programmable
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 80 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. ? size bits of an enabled endpoint (ffosz[3:0]) ? isochronous bit of an enabled endpoint (ffoiso). remark: register changes that affect the allocation of the shared fifo storage among endpoints must not be made while valid data is present in any fifo of the enabled endpoints. such changes will render all fifo contents unde?ned . each programmable fifo can be con?gured independently via its ecr, but the total physical size of all enabled endpoints (in plus out) must not exceed 2462 bytes (512 bytes for non-isochronous fifos). ta b l e 6 8 shows an example of a con?guration ?tting in the maximum available space of 2462 bytes. the total number of logical bytes in the example is 1311. the physical storage capacity used for double buffering is managed by the device hardware and is transparent to the user. table 67: programmable fifo size ffosz[3:0] non-isochronous isochronous 0000 8 bytes 16 bytes 0001 16 bytes 32 bytes 0010 32 bytes 48 bytes 0011 64 bytes 64 bytes 0100 reserved 96 bytes 0101 reserved 128 bytes 0110 reserved 160 bytes 0111 reserved 192 bytes 1000 reserved 256 bytes 1001 reserved 320 bytes 1010 reserved 384 bytes 1011 reserved 512 bytes 1100 reserved 640 bytes 1101 reserved 768 bytes 1110 reserved 896 bytes 1111 reserved 1023 bytes table 68: memory con?guration example physical size (bytes) logical size (bytes) endpoint description 64 64 control in (64-byte ?xed) 64 64 control out (64-byte ?xed) 2046 1023 double-buffered 1023-byte isochronous endpoint 16 16 16-byte interrupt out 16 16 16-byte interrupt in 128 64 double-buffered 64-byte bulk out 128 64 double-buffered 64-byte bulk in
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 81 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 11.3.4 endpoint initialization in response to the standard usb request, set interface, the ?rmware must program all 16 ecrs of the isp1161a1s dc in sequence (see ta b l e 6 6 ), whether the endpoints are enabled or not. the hardware will then automatically allocate fifo storage space. if all endpoints have been con?gured successfully, the ?rmware must return an empty packet to the control in endpoint to acknowledge success to the host. if there are errors in the endpoint con?guration, the ?rmware must stall the control in endpoint. when reset by hardware or via the usb bus, the isp1161a1s dc disables all endpoints and clears all ecrs, except for the control endpoint which is ?xed and always enabled. endpoint initialization can be done at any time; however, it is valid only after enumeration. 11.3.5 endpoint i/o mode access when an endpoint event occurs (a packet is transmitted or received), the associated endpoint interrupt bits (epn) of the dcinterrupt register will be set by the sie. the ?rmware then responds to the interrupt and selects the endpoint for processing. the endpoint interrupt bit will be cleared by reading the dcendpointstatus register (esr). the esr also contains information on the status of the endpoint buffer. for an out (receive) endpoint, the packet length and packet data can be read from the isp1161a1s dc using the read buffer command. when the whole packet has been read, the ?rmware sends a clear buffer command to enable the reception of new packets. for an in (transmit) endpoint, the packet length and data to be sent can be written to the isp1161a1s dc using the write buffer command. when the whole packet has been written to the buffer, the ?rmware sends a validate buffer command to enable data transmission to the host. 11.3.6 special actions on control endpoints control endpoints require special ?rmware actions. the arrival of a setup packet ?ushes the in buffer and disables the validate buffer and clear buffer commands for the control in and out endpoints. the microcontroller needs to re-enable these commands by sending an acknowledge setup command. this ensures that the last setup packet stays in the buffer and that no packets can be sent back to the host until the microcontroller has explicitly acknowledged that it has seen the setup packet.
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 82 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 11.4 suspend and resume 11.4.1 suspend conditions the isp1161a1 dc detects a usb suspend status when a constant idle state is present on the usb bus for more than 3 ms. the bus-powered devices that are suspended must not consume more than 500 m a of current. this is achieved by shutting down power to system components or supplying them with a reduced voltage. the steps leading up to suspend status are as follows: 1. on detecting a wakeup-to-suspend transition, the isp1161a1 dc sets bit suspnd in the dcinterrupt register. this will generate an interrupt if bit iesusp in the dcinterruptenable register is set. 2. when the ?rmware detects a suspend condition, it must prepare all system components for the suspend state: a. all signals connected to the isp1161a1 dc must enter appropriate states to meet the power consumption requirements of the suspend state. b. all input pins of the isp1161a1 dc must have a cmos low or high level. 3. in the interrupt service routine, the ?rmware must check the current status of the usb bus. when bit bustatus in the dcinterrupt register is logic 0, the usb bus has left the suspend mode and the process must be aborted. otherwise, the next step can be executed. 4. to meet the suspend current requirements for a bus-powered device, the internal clocks must be switched off by clearing bit clkrun in the dchardwarecon?guration register. 5. when the ?rmware has set and cleared bit gosusp in the dcmode register, the isp1161a1 enters the suspend state. in powered-off application, the isp1161a1 dc asserts output suspend and switches off the internal clocks after 2 ms. figure 38 shows a typical timing diagram.
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 83 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. in figure 38 : ? a : indicates the point at which the usb bus enters the idle state. ? b : indicates resume condition, which can be a 20 ms k-state on the usb bus, a high level on pin d_wakeup, or a low level on pin cs. ? c : indicates remote wake-up. the isp1161a1 will drive a k-state on the usb bus for 10 ms after pin d_wakeup goes high or pin cs goes low. ? d : after detecting the suspend interrupt, set and clear bit gosusp in the dcmode register. powered-off application: figure 39 shows a typical bus-powered modem application using the isp1161a1. the suspend output switches off power to the microcontroller and other external circuits during the suspend state. the isp1161a1 dc is woken up through the usb bus (global resume) or by the ring detection circuit on the telephone line. fig 38. suspend and resume timing. 004aaa359 int_n > 5 ms suspend interrupt usb bus gosusp wakeup suspend idle state 10 ms k-state > 3 ms 1.8 ms to 2.2 ms 0.5 ms to 3.5 ms resume interrupt a c d b fig 39. suspend and wakeup signals in a powered-off modem application. wakeup 8031 rst ring detection isp1161a dp dm usb v bus v bus v cc line 004aaa674 suspend
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 84 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 11.4.2 resume conditions a wake-up from the suspend state is initiated either by the usb host or by the application: ? usb host : drives a k-state on the usb bus (global resume) ? application : remote wake-up through a high level on input wakeup or a low level on input cs, if enabled using bit wkupcs in the dchardwarecon?guration register. wake-up on cs will work only if v bus is present. the steps of a wake-up sequence are as follows: 1. the internal oscillator and the pll multiplier are re-enabled. when stabilized, the clock signals are routed to all internal circuits of the isp1161a1. 2. the suspend output is deasserted, and bit resume in the dcinterrupt register is set. this will generate an interrupt if bit ieresm in the dcinterruptenable register is set. 3. maximum 15 ms after starting the wake-up sequence, the isp1161a1 dc resumes its normal functionality. 4. in case of a remote wake-up, the isp1161a1 dc drives a k-state on the usb bus for 10 ms. 5. following the deassertion of output suspend, the application restores itself and other system components to the normal operating mode. 6. after wake-up, the internal registers of the isp1161a1 dc are write-protected to prevent corruption by inadvertent writing during power-up of external components. the ?rmware must send an unlock device command to the isp1161a1 dc to restore its full functionality. 11.4.3 control bits in suspend and resume table 69: summary of control bits register bit function dcinterrupt suspnd a transition from awake to the suspend state was detected bustatus monitors usb bus status (logic 1 = suspend); used when interrupt is serviced resume a transition from suspend to the resume state was detected dcinterrupt enable iesusp enables output int to signal the suspend state ieresm enables output int to signal the resume state dcmode softct enables softconnect pull-up resistor to usb bus gosusp a high-to-low transition enables the suspend state dchardware con?guration extpul selects internal (softconnect) or external pull-up resistor wkupcs enables wake-up on low level of input cs pwroff selects powered-off mode during the suspend state dcunlock all sending data aa37h unlocks the internal registers for writing after a resume
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 85 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 12. dc dma transfer direct memory access (dma) is a method to transfer data from one location to another in a computer system, without intervention of the central processor unit (cpu). many different implementations of dma exist. the isp1161a1 dc supports two methods: ? 8237 compatible mode : based on the dma subsystem of the ibm personal computers (pc, at and all its successors and clones); this architecture uses the intel 8237 dma controller and has separate address spaces for memory and i/o ? dack-only mode : based on the dma implementation in some embedded risc processors, which has a single address space for both memory and i/o. the isp1161a1s dc supports dma transfer for all 14 con?gurable endpoints (see ta b l e 6 6 ). only one endpoint at a time can be selected for dma transfer. the dma operation of the isp1161a1s dc can be interleaved with normal i/o mode access to other endpoints. the following features are supported: ? single-cycle or burst transfers (up to 16 bytes per cycle) ? programmable transfer direction (read or write) ? multiple end-of-transfer (eot) sources: external pin, internal conditions, short/empty packet ? programmable signal levels on pins dreq2 and eot. 12.1 selecting an endpoint for dma transfer the target endpoint for dma access is selected via bits epdix[3:0] in the dcdmacon?guration register, as shown in ta b l e 7 0 . the transfer direction (read or write) is automatically set by bit epdir in the associated ecr, to match the selected endpoint type (out endpoint: read; in endpoint: write). asserting input d a ck2 automatically selects the endpoint speci?ed in the dcdmacon?guration register, regardless of the current endpoint used for i/o mode access. table 70: endpoint selection for dma transfer endpoint identi?er epidx[3:0] transfer direction epdir = 0 epdir = 1 1 0010 out: read in: write 2 0011 out: read in: write 3 0100 out: read in: write 4 0101 out: read in: write 5 0110 out: read in: write 6 0111 out: read in: write 7 1000 out: read in: write 8 1001 out: read in: write 9 1010 out: read in: write
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 86 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 12.2 8237 compatible mode the 8237 compatible dma mode is selected by clearing bit dakoly in the dchardwarecon?guration register (see ta b l e 8 2 ). the pin functions for this mode are shown in ta b l e 7 1 . the dma subsystem of an ibm compatible pc is based on the intel 8237 dma controller. it operates as a ?y-by dma controller: the data is not stored in the dma controller, but it is transferred between an i/o port and a memory address. a typical example of the isp1161a1s dc in 8237 compatible dma mode is given in figure 40 . the 8237 has two control signals for each dma channel: dreq (dma request) and d a ck (dma acknowledge). general control signals are hrq (hold request) and hlda (hold acknowledge). the bus operation is controlled via memr (memory read), memw (memory write), ior (i/o read) and io w (i/o write). 10 1011 out: read in: write 11 1100 out: read in: write 12 1101 out: read in: write 13 1110 out: read in: write 14 1111 out: read in: write table 70: endpoint selection for dma transfer continued endpoint identi?er epidx[3:0] transfer direction epdir = 0 epdir = 1 table 71: 8237 compatible mode: pin functions symbol description i/o function dreq2 dcs dma request o isp1161a1s dc requests a dma transfer d a ck2 dcs dma acknowledge i dma controller con?rms the transfer eot end of transfer i dma controller terminates the transfer rd read strobe i instructs the isp1161a1s dc to put data on the bus wr write strobe i instructs the isp1161a1s dc to get data from the bus fig 40. isp1161a1s device controller in 8237 compatible dma mode. d0 to d15 cpu 004aaa185 ram isp1161a1 device controller dma controller 8237 dreq2 dack2 dreq hrq hlda hrq hlda dack ior iow memr memw rd wr
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 87 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. the following example shows the steps which occur in a typical dma transfer: 1. the isp1161a1s dc receives a data packet in one of its endpoint fifos; the packet must be transferred to memory address 1234h. 2. the isp1161a1s dc asserts the dreq2 signal requesting the 8237 for a dma transfer. 3. the 8237 asks the cpu to release the bus by asserting the hrq signal. 4. after completing the current instruction cycle, the cpu places the bus control signals ( memr, memw, ior and io w) and the address lines in three-state and asserts hlda to inform the 8237 that it has control of the bus. 5. the 8237 now sets its address lines to 1234h and activates the memw and ior control signals. 6. the 8237 asserts d a ck to inform the isp1161a1s dc that it will start a dma transfer. 7. the isp1161a1s dc now places the word to be transferred on the data bus lines, because its rd signal was asserted by the 8237. 8. the 8237 waits one dma clock period and then de-asserts memw and ior. this latches and stores the word at the desired memory location. it also informs the isp1161a1s dc that the data on the bus lines has been transferred. 9. the isp1161a1s dc de-asserts the dreq2 signal to indicate to the 8237 that dma is no longer needed. in single cycle mode this is done after each word, in burst mode following the last transferred word of the dma cycle. 10. the 8237 de-asserts the d a ck output indicating that the isp1161a1s dc must stop placing data on the bus. 11. the 8237 places the bus control signals ( memr, memw, ior and io w) and the address lines in three-state and de-asserts the hrq signal, informing the cpu that it has released the bus. 12. the cpu acknowledges control of the bus by de-asserting hlda. after activating the bus control lines ( memr, memw, ior and io w) and the address lines, the cpu resumes the execution of instructions. for a typical bulk transfer the above process is repeated, once for each byte. after each byte the address register in the dma controller is incremented and the byte counter is decremented. when using 16-bit dma the number of transfers is 32, and address incrementing and byte counter decrementing is done by 2 for each word. 12.3 dack-only mode the dack-only dma mode is selected by setting bit dakoly in the dchardwarecon?guration register (see ta b l e 8 2 ). the pin functions for this mode are shown in ta b l e 7 2 . a typical example of the isp1161a1s dc in dack-only dma mode is given in figure 41 .
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 88 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. in the dack-only mode, the isp1161a1s dc uses the d a ck2 signal as a data strobe. input signals rd and wr are ignored. this mode is used in cpu systems that have a single address space for memory and i/o access. such systems have no separate memw and memr signals: the rd and wr signals are also used as memory data strobes. 12.4 end-of-transfer conditions 12.4.1 bulk endpoints a dma transfer to/from a bulk endpoint can be terminated by any of the following conditions (bit names refer to the dcdmacon?guration register, see ta b l e 8 6 ): ? an external end-of-transfer signal occurs on input eot ? the dma transfer completes as programmed in the dcdmacounter register (cntren = 1) ? a short packet is received on an enabled out endpoint (shortp = 1) ? dma operation is disabled by clearing bit dmaen. external eot: when reading from an out endpoint, an external eot will stop the dma operation and clear any remaining data in the current fifo. for a double- buffered endpoint the other (inactive) buffer is not affected. when writing to an in endpoint, an eot will stop the dma operation and the data packet in the fifo (even if it is smaller than the maximum packet size) will be sent to the usb host at the next in token. table 72: dack-only mode: pin functions symbol description i/o function dreq2 dcs dma request o isp1161a1 dc requests a dma transfer d a ck2 dcs dma acknowledge i dma controller con?rms the transfer; also functions as data strobe eot end-of-transfer i dma controller terminates the transfer rd read strobe i not used wr write strobe i not used fig 41. isp1161a1s device controller in dack-only dma mode. ram isp1161a1 device controller dma controller cpu dreq2 dack2 hrq hlda hrq hlda dreq dack rd wr 004aaa186 d0 to d15
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 89 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. dcdmacounter register: an eot from the dcdmacounter register is enabled by setting bit cntren in the dcdmacon?guration register. the isp1161a1 has a 16-bit dcdmacounter register, which speci?es the number of bytes to be transferred. when dma is enabled (dmaen = 1), the internal dma counter is loaded with the value from the dcdmacounter register. when the internal counter completes the transfer as programmed in the dcdmacounter, an eot condition is generated and the dma operation stops. short packet: normally, the transfer byte count must be set via a control endpoint before any dma transfer takes place. when a short packet has been enabled as eot indicator (shortp = 1), the transfer size is determined by the presence of a short packet in the data. this mechanism permits the use of a fully autonomous data transfer protocol. when reading from an out endpoint, reception of a short packet at an out token will stop the dma operation after transferring the data bytes of this packet. [1] the dma transfer stops. however, no interrupt is generated. 12.4.2 isochronous endpoints a dma transfer to/from an isochronous endpoint can be terminated by any of the following conditions (bit names refer to the dcdmacon?guration register, see ta b l e 8 6 ): ? an external end-of-transfer signal occurs on input eot ? the dma transfer completes as programmed in the dcdmacounter register (cntren = 1) ? an end-of-packet (eop) signal is detected ? dma operation is disabled by clearing bit dmaen. table 73: summary of eot conditions for a bulk endpoint eot condition out endpoint in endpoint eot input eot is active eot is active dcdmacounter register transfer completes as programmed in the dcdmacounter register transfer completes as programmed in the dcdmacounter register short packet short packet is received and transferred counter reaches zero in the middle of the buffer bit dmaen in dcdmacon?guration register dmaen = 0 [1] dmaen = 0 [1] table 74: recommended eot usage for isochronous endpoints eot condition out endpoint in endpoint eot input active do not use preferred dma counter register zero do not use preferred end-of-packet preferred do not use
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 90 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13. dc commands and registers the functions and registers of the isp1161a1s dc are accessed via commands, which consist of a command code followed by optional data bytes (read or write action). an overview of the available commands and registers is given in ta b l e 7 5 . a complete access consists of two phases: 1. command phase : when address bit a0 = 1, the dc interprets the data on the lower byte of the bus (bits d7 to d0) as a command code. commands without a data phase are executed immediately. 2. data phase (optional) : when address bit a0 = 0, the dc transfers the data on the bus to or from a register or endpoint fifo. multi-byte registers are accessed least signi?cant byte/word ?rst. as the isp1161a1 dcs data bus is 16 bits wide: ? the upper byte (bits d15 to d8) in command phase, or the unde?ned byte in data phase and is ignored. ? the access of registers is word-aligned: byte access is not allowed. ? if the packet length is odd, the upper byte of the last word in an in endpoint buffer is not transmitted to the host. when reading from an out endpoint buffer, the upper byte of the last word must be ignored by the ?rmware. the packet length is stored in the ?rst 2 bytes of the endpoint buffer. table 75: dc command and register summary name destination code (hex) transaction [1] reference initialization commands write control out con?guration dcendpointcon?guration register endpoint 0 out 20 write 1 word section 13.1.1 on page 92 write control in con?guration dcendpointcon?guration register endpoint 0 in 21 write 1 word write endpoint n con?guration (n = 1 to 14) dcendpointcon?guration register endpoint 1 to 14 22 to 2f write 1 word read control out con?guration dcendpointcon?guration register endpoint 0 out 30 read 1 word read control in con?guration dcendpointcon?guration register endpoint 0 in 31 read 1 word read endpoint n con?guration (n = 1 to 14) dcendpointcon?guration register endpoint 1 to 14 32 to 3f read 1 word write/read device address dcaddress register b6/b7 write/read 1 word section 13.1.2 on page 93 write/read mode register dcmode register b8/b9 write/read 1 word section 13.1.3 on page 94 write/read hardware con?guration dchardwarecon?guration register ba/bb write/read 1 word section 13.1.4 on page 94 write/read dcinterruptenable register dcinterruptenable register c2/c3 write/read 2 words section 13.1.5 on page 96 write/read dma con?guration dcdmacon?guration register f0/f1 write/read 1 word section 13.1.6 on page 97
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 91 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. write/read dma counter dcdmacounter register f2/f3 write/read 1 word section 13.1.7 on page 98 reset device resets all registers f6 - section 13.1.8 on page 99 data ?ow commands write control out buffer illegal: endpoint is read-only (00) - section 13.2.1 on page 99 write control in buffer fifo endpoint 0 in 01 n 64 bytes write endpoint n buffer (n = 1 to 14) fifo endpoint 1 to 14 (in endpoints only) 02 to 0f isochronous: n 1023 bytes interrupt/bulk: n 64 bytes read control out buffer fifo endpoint 0 out 10 n 64 bytes read control in buffer illegal: endpoint is write-only (11) - read endpoint n buffer (n = 1 to 14) fifo endpoint 1 to 14 (out endpoints only) 12 to 1f isochronous: n 1023 bytes [6] interrupt/bulk: n 64 bytes stall control out endpoint endpoint 0 out 40 - stall control in endpoint endpoint 0 in 41 - stall endpoint n (n = 1 to 14) endpoint 1 to 14 42 to 4f - read control out status dcendpointstatus register endpoint 0 out 50 read 1 word section 13.2.2 on page 100 read control in status dcendpointstatus register endpoint 0 in 51 read 1 word read endpoint n status (n = 1 to 14) dcendpointstatus register n endpoint 1 to 14 52 to 5f read 1 word validate control out buffer illegal: in endpoints only [2] (60) - section 13.2.4 on page 102 validate control in buffer fifo endpoint 0 in [2] 61 none validate endpoint n buffer (n = 1 to 14) fifo endpoint 1 to 14 (in endpoints only) [2] 62 to 6f none clear control out buffer fifo endpoint 0 out 70 none section 13.2.5 on page 102 clear control in buffer illegal [3] (71) - clear endpoint n buffer (n = 1 to 14) fifo endpoint 1 to 14 (out endpoints only) [3] 72 to 7f none unstall control out endpoint endpoint 0 out 80 - section 13.2.3 on page 101 unstall control in endpoint endpoint 0 in 81 - unstall endpoint n (n = 1 to 14) endpoint 1 to 14 82 to 8f - check control out status [4] dcendpointstatusimage register endpoint 0 out d0 read 1 word section 13.2.6 on page 102 check control in status [4] dcendpointstatusimage register endpoint 0 in d1 read 1 word check endpoint n status (n = 1 to 14) [4] dcendpointstatusimage register n endpoint 1 to 14 d2 to df read 1 word table 75: dc command and register summary continued name destination code (hex) transaction [1] reference
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 92 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] with n representing the number of bytes, the number of words for 16-bit bus width is: (n + 1)/2. [2] validating an out endpoint buffer causes unpredictable behavior of the isp1161a1s dc. [3] clearing an in endpoint buffer causes unpredictable behavior of the isp1161a1s dc. [4] reads a copy of the status register: executing this command does not clear any status bits or interrupt bits. [5] when accessing an 8-bit register in 16-bit mode, the upper byte is invalid. [6] during isochronous transfer in 16-bit mode, because n 1023, the ?rmware must take care of the upper byte. 13.1 initialization commands initialization commands are used during the enumeration process of the usb network. these commands are used to con?gure and enable the embedded endpoints. they also serve to set the usb assigned address of the isp1161a1s dc and to perform a device reset. 13.1.1 dcendpointcon?guration register (r/w: 30hC3fh/20hC2fh) this command is used to access the endpoint con?guration register (ecr) of the target endpoint. it de?nes the endpoint type (isochronous or bulk/interrupt), direction (out/in), fifo size and buffering scheme. it also enables the endpoint fifo. the register bit allocation is shown in ta b l e 7 6 . a bus reset will disable all endpoints. the allocation of fifo memory only takes place after all 16 endpoints have been con?gured in sequence (from endpoint 0 out to endpoint 14). although the control endpoints have ?xed con?gurations, they must be included in the initialization sequence and be con?gured with their default values (see ta b l e 6 6 ). automatic fifo allocation starts when endpoint 14 has been con?gured. remark: if any change is made to an endpoint con?guration which affects the allocated memory (size, enable/disable), the fifo memory contents of all endpoints becomes invalid. therefore, all valid data must be removed from enabled endpoints before changing the con?guration. code (hex): 20 to 2f write (control out, control in, endpoint 1 to 14) code (hex): 30 to 3f read (control out, control in, endpoint 1 to 14) acknowledge setup endpoint 0 in and out f4 none section 13.2.7 on page 103 general commands read control out error code dcerrorcode register endpoint 0 out a0 read 1 word [5] section 13.3.1 on page 103 read control in error code dcerrorcode register endpoint 0 in a1 read 1 word [5] read endpoint n error code (n = 1 to 14) dcerrorcode register endpoint 1 to 14 a2 to af read 1 word [5] unlock device all registers with write access b0 write 1 word section 13.3.2 on page 104 write/read scratch register dcscratch register b2/b3 write/read 1 word section 13.3.3 on page 105 read frame number dcframenumber register b4 read 1 word section 13.3.4 on page 105 read chip id dcchipid register b5 read 1 word section 13.3.5 on page 106 read interrupt register dcinterrupt register c0 read 2 words section 13.3.6 on page 107 table 75: dc command and register summary continued name destination code (hex) transaction [1] reference
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 93 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. transaction write/read 1 word 13.1.2 dcaddress register (r/w: b7h/b6h) this command is used to set the usb assigned address in the dcaddress register and enable the usb device. the dcaddress register bit allocation is shown in ta b l e 7 8 . a usb bus reset sets the device address to 00h (internally) and enables the device. the value of the dcaddress register (accessible by the microcontroller) is not altered by the bus reset. in response to the standard usb request, set address, the ?rmware must issue a write device address command, followed by sending an empty packet to the host. the new device address is activated when the host acknowledges the empty packet. code (hex): b6/b7 write/read dcaddress register transaction write/read 1 word table 76: dcendpointcon?guration register: bit allocation bit 7 6 5 4 3 2 1 0 symbol fifoen epdir dblbuf ffoiso ffosz[3:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 77: dcendpointcon?guration register: bit description bit symbol description 7 fifoen a logic 1 indicates an enabled fifo with allocated memory. a logic 0 indicates a disabled fifo (no bytes allocated). 6 epdir this bit de?nes the endpoint direction (0 = out, 1 = in); it also determines the dma transfer direction (0 = read, 1 = write). 5 dblbuf a logic 1 indicates that this endpoint has double buffering. 4 ffoiso a logic 1 indicates an isochronous endpoint. a logic 0 indicates a bulk or interrupt endpoint. 3 to 0 ffosz[3:0] selects the fifo size according to ta b l e 6 7 table 78: dcaddress register: bit allocation bit 7 6 5 4 3 2 1 0 symbol deven devadr[6:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 79: dcaddress register: bit description bit symbol description 7 deven a logic 1 enables the device. 6 to 0 devadr[6:0] this ?eld speci?es the usb device address.
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 94 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13.1.3 dcmode register (r/w: b9h/b8h) this command is used to access the isp1161a1s dcmode register, which consists of 1 byte (for bit allocation: see ta b l e 7 9 ). in 16-bit bus mode the upper byte is ignored. the dcmode register controls the dma bus width, resume and suspend modes, interrupt activity and softconnect operation. it can be used to enable debug mode, where all errors and not acknowledge (nak) conditions will generate an interrupt. code (hex): b8/b9 write/read mode register transaction write/read 1 word [1] unchanged by a bus reset. 13.1.4 dchardwarecon?guration register (r/w: bbh/bah) this command is used to access the dchardwarecon?guration register, which consists of 2 bytes. the ?rst (lower) byte contains the device con?guration and control values, the second (upper) byte holds the clock control bits and the clock division factor. the bit allocation is given in ta b l e 8 2 . a bus reset will not change any of the programmed bit values. table 80: dcmode register: bit allocation bit 7 6 5 4 3 2 1 0 symbol dmawd reserved gosusp reserved intena dbgmod reserved softct reset 0 [1] 0000 [1] 0 [1] 0 [1] 0 [1] access r/w r/w r/w r/w r/w r/w r/w r/w table 81: dcmode register: bit description bit symbol description 7 dmawd a logic 1 selects 16-bit dma bus width (bus con?guration modes 0 and 2). a logic 0 selects 8-bit dma bus width. bus reset value: unchanged. 6 - reserved 5 gosusp writing a logic 1 followed by a logic 0 will activate suspend mode. 4 - reserved 3 intena a logic 1 enables all dc interrupts. bus reset value: unchanged; for details, see section 8.6.3 . 2 dbgmod a logic 1 enables debug mode where all naks and errors will generate an interrupt. a logic 0 selects normal operation, where interrupts are generated on every ack (bulk endpoints) or after every data transfer (isochronous endpoints). bus reset value: unchanged. 1 - reserved 0 softct a logic 1 enables softconnect (see section 7.5 ). this bit is ignored if extpul = 1 in the dchardwarecon?guration register (see ta b l e 8 2 ). bus reset value: unchanged.
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 95 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. the dchardwarecon?guration register controls the connection to the usb bus, clock activity and power supply during suspend state, output clock frequency, dma operating mode and pin con?gurations (polarity, signalling mode). code (hex): ba/bb write/read dchardwarecon?guration register transaction write/read 1 word table 82: dchardwarecon?guration register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved extpul nolazy clkrun clkdiv[3:0] reset 00100011 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol dakoly drqpol dakpol eotpol wkupcs pwroff intlvl intpol reset 01000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 83: dchardwarecon?guration register: bit description bit symbol description 15 - reserved 14 extpul a logic 1 indicates that an external 1.5 k w pull-up resistor is used on pin d + and that softconnect is not used. bus reset value: unchanged. 13 nolazy a logic 1 disables output on pin clkout of the lazyclock frequency (100 khz 50 %) during suspend state. a logic 0 causes pin clkout to switch to lazyclock output after approximately 2 ms delay, following the setting of bit gosusp in the dcmode register. bus reset value: unchanged. 12 clkrun a logic 1 indicates that the internal clocks are always running, even during suspend state. a logic 0 switches off the internal oscillator and pll, when they are not needed. during suspend state this bit must be made logic 0 to meet the suspend current requirements. the clock is stopped after a delay of approximately 2 ms, following the setting of bit gosusp in the dcmode register. bus reset value: unchanged. 11 to 8 clkdiv[3:0] this ?eld speci?es the clock division factor n, which controls the clock frequency on output clkout. the output frequency in mhz is given by 48 / (n + 1). the clock frequency range is 3 mhz to 48 mhz ( n=0to 15) with a reset value of 12 mhz (n = 3). the hardware design guarantees no glitches during frequency change. bus reset value: unchanged. 7 dakoly a logic 1 selects dack-only dma mode. a logic 0 selects 8237 compatible dma mode. bus reset value: unchanged. 6 drqpol selects dreq2 pin signal polarity (0 = active low, 1 = active high). bus reset value: unchanged. 5 dakpol selects d a ck2 pin signal polarity (0 = active low). bus reset value: unchanged. 4 eotpol selects eot pin signal polarity (0 = active low, 1 = active high). bus reset value: unchanged.
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 96 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13.1.5 dcinterruptenable register (r/w: c3h/c2h) this command is used to individually enable or disable interrupts from all endpoints, as well as interrupts caused by events on the usb bus (sof, sof lost, eot, suspend, resume, reset). that is, if an interrupt event occurs while the interrupt is not enabled, nothing will be seen on the interrupt pin. even if you then enable the interrupt during the interrupt event, there will still be no interrupt seen on the interrupt pin, see figure 42 . the dcinterrupt register will not register any interrupt, if it is not already enabled using the dcinterruptenable register. the dcinterruptenable register is not an interrupt mask register. a bus reset will not change any of the programmed bit values. the command accesses the dcinterruptenable register, which consists of 4 bytes. the bit allocation is given in ta b l e 8 4 . remark: for details on interrupt control, see section 8.6.3 . 3 wkupcs a logic 1 enables remote wake-up via a low level on input pin cs (v bus must be present for wake-up on cs). bus reset value: unchanged. 2 pwroff a logic 1 enables powering-off during suspend state. output d_suspend pin is con?gured as a power switch control signal for external devices (high during suspend). this value should always be initialized to logic 1. bus reset value: unchanged. 1 intlvl selects the interrupt signalling mode on output pin int2 (0 = level, 1 = pulsed). in pulsed mode an interrupt produces an 166 ns pulse. see section 8.6.3 for details. bus reset value: unchanged. 0 intpol selects int2 pin signal polarity (0 = active low, 1 = active high). bus reset value: unchanged. table 83: dchardwarecon?guration register: bit description continued bit symbol description pin int2: high = de-assert; low = assert; intena = 1. fig 42. interrupt pin waveform. int2 pin interrupt event occurs interrupt event occurs dcinterruptenable register disabled dcinterruptenable register enabled interrupt is cleared 004aaa197
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 97 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. code (hex): c2/c3 write/read dcinterruptenable register transaction write/read 2 words 13.1.6 dcdmacon?guration register (r/w: f1h/f0h) this command de?nes the dma con?guration of the isp1161a1s dc and enables/disables dma transfers. the command accesses the dcdmacon?guration register, which consists of 2 bytes. the bit allocation is given in ta b l e 8 6 . a bus reset will clear bit dmaen (dma disabled), all other bits remain unchanged. code (hex): f0/f1 write/read dma con?guration transaction write/read 1 word table 84: dcinterruptenable register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset 00h access r/w bit 23 22 21 20 19 18 17 16 symbol iep14 iep13 iep12 iep11 iep10 iep9 iep8 iep7 reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol iep6 iep5 iep4 iep3 iep2 iep1 iep0in iep0out reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved sp_ieeot iepsof iesof ieeot iesusp ieresm ierst reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 85: dcinterruptenable register: bit description bit symbol description 31 to 24 - reserved; must write logic 0 23 to 10 iep14 to iep1 a logic 1 enables interrupts from the indicated endpoint. 9 iep0in a logic 1 enables interrupts from the control in endpoint. 8 iep0out a logic 1 enables interrupts from the control out endpoint. 7 - reserved 6 sp_ieeot a logic 1 enables interrupt upon detection of a short packet. 5 iepsof a logic 1 enables 1 ms interrupts upon detection of pseudo sof. 4 iesof a logic 1 enables interrupt upon sof detection. 3 ieeot a logic 1 enables interrupt upon eot detection. 2 iesusp a logic 1 enables interrupt upon detection of suspend state. 1 ieresm a logic 1 enables interrupt upon detection of a resume state. 0 ierst a logic 1 enables interrupt upon detection of a bus reset.
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 98 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] unchanged by a bus reset. for selecting an endpoint for device dma transfer, see section 11.2 . 13.1.7 dcdmacounter register (r/w: f3h/f2h) this command accesses the dcdmacounter register. the bit allocation is given in ta b l e 8 8 . writing to the register sets the number of bytes for a dma transfer. reading the register returns the number of remaining bytes in the current transfer. a bus reset will not change the programmed bit values. table 86: dcdmacon?guration register: bit allocation bit 15 14 13 12 11 10 9 8 symbol cntren shortp reserved reserved reserved reserved reserved odd_ even_ind reset 0 [1] 0 [1] 0 [1] 0 [1] 0 [1] 0 [1] 0 [1] 0 access r/w r/w r/w r/w r/w r/w r/w r bit 7 6 5 4 3 2 1 0 symbol epdix[3:0] dmaen reserved burstl[1:0] reset 0 [1] 0 [1] 0 [1] 0 [1] 000 [1] 0 [1] access r/w r/w r/w r/w r/w r/w r/w r/w table 87: dcdmacon?guration register: bit description bit symbol description 15 cntren a logic 1 enables the generation of an eot condition, when the dma counter register reaches zero. bus reset value: unchanged. 14 shortp a logic 1 enables short/empty packet mode. when receiving (out endpoint) a short/empty packet an eot condition is generated. when transmitting (in endpoint), this bit should be cleared. bus reset value: unchanged. 13 to 9 - reserved 8 odd_even_ ind this bit is logic 0 when the last dma access is a byte (lsb byte valid; msb byte invalid). this bit is logic 1 when the last dma access is a word (lsb byte valid; msb byte invalid). 7 to 4 epdix[3:0] indicates the destination endpoint for dma, see ta b l e 7 0 . 3 dmaen writing a logic 1 enables dma transfer, a logic 0 forces the end of an ongoing dma transfer. reading this bit indicates whether dma is enabled (0 = dma stopped, 1 = dma enabled). this bit is cleared by a bus reset. 2 - reserved 1 to 0 burstl[1:0] selects the dma burst length: 00 single-cycle mode (1 byte) 01 burst mode (4 bytes) 10 burst mode (8 bytes) 11 burst mode (16 bytes). bus reset value: unchanged.
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 99 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. the internal dma counter is automatically reloaded from the dcdmacounter register when dma is re-enabled (dmaen = 1). see section 13.1.6 for more details. code (hex): f2/f3 write/read dcdmacounter register transaction write/read 1 word 13.1.8 reset device (f6h) this command resets the isp1161a1 dc in the same way as an external hardware reset via input reset. all registers are initialized to their reset values. code (hex): f6 reset the device transaction none 13.2 data ?ow commands data ?ow commands are used to manage the data transmission between the usb endpoints and the system microprocessor. much of the data ?ow is initiated via an interrupt to the microprocessor. the data ?ow commands are used to access the endpoints and determine whether the endpoint fifos contain valid data. remark: the in buffer of an endpoint contains input data for the host, the out buffer receives output data from the host. 13.2.1 write/read endpoint buffer (r/w: 10h,12h-1fh/01hC0fh) this command is used to access endpoint fifo buffers for reading or writing. first, the buffer pointer is reset to the beginning of the buffer. following the command, a maximum of (m + 1) words can be written or read, with m given by (n + 1)/2, n representing the size of the endpoint buffer. after each read/write action the buffer pointer is automatically incremented by 2. in dma access, the ?rst word (the packet length) is skipped: transfers start at the second word of the endpoint buffer. when reading, the isp1161a1 dc can detect the last word via the end of packet (eop) condition. when writing to a bulk/interrupt endpoint, the endpoint buffer must be completely ?lled before sending the data to the host. exception: when a dma transfer is stopped by an external eot condition, the current buffer content (full or not) is sent to the host. table 88: dcdmacounter register: bit allocation bit 15 14 13 12 11 10 9 8 symbol dmacr[15:8] reset 00h access r/w bit 7 6 5 4 3 2 1 0 symbol dmacr[7:0] reset 00h access r/w table 89: dcdmacounter register: bit description bit symbol description 15 to 0 dmacr[15:0] dma counter register
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 100 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. remark: reading data after a write endpoint buffer command or writing data after a read endpoint buffer command will cause unpredictable behavior of the isp1161a1 dc. code (hex): 01 to 0f write (control in, endpoint 1 to 14) code (hex): 10, 12 to 1f read (control out, endpoint 1 to 14) transaction write/read maximum (m + 1) words (isochronous endpoint: n 1023, bulk/interrupt endpoint: n 32) the data in the endpoint fifo must be organized as shown in ta b l e 9 0 . an example of endpoint fifo access is given ta b l e 9 1 . remark: there is no protection against writing or reading past a buffers boundary or against writing into an out buffer or reading from an in buffer. any of these actions could cause an incorrect operation. data residing in an out buffer are only meaningful after a successful transaction. exception: during dma access of a double-buffered endpoint, the buffer pointer automatically points to the secondary buffer after reaching the end of the primary buffer. 13.2.2 dcendpointstatus register (r: 50hC5fh) this command is used to read the status of an endpoint fifo. the command accesses the dcendpointstatus register, the bit allocation of which is shown in ta b l e 9 2 . reading the dcendpointstatus register will clear the interrupt bit set for the corresponding endpoint in the dcinterrupt register (see table 108 ). all bits of the dcendpointstatus register are read-only. bit epstal is controlled by the stall/unstall commands and by the reception of a setup token (see section 13.2.3 ). code (hex): 50 to 5f read (control out, control in, endpoint 1 to 14) transaction read 1 word table 90: endpoint fifo organization word # description 0 (lower byte) packet length (lower byte) 0 (upper byte) packet length (upper byte) 1 (lower byte) data byte 1 1 (upper byte) data byte 2 :: m = (n + 1)/2 data byte n table 91: example of endpoint fifo access a0 phase bus lines word # description 1 command d[7:0] - command code (00h to 1fh) d[15:8] - ignored 0 data d[15:0] 0 packet length 0 data d[15:0] 1 data word 1 (data byte 2, data byte 1) 0 data d[15:0] 2 data word 2 (data byte 4, data byte 3) :::::
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 101 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13.2.3 stall endpoint/unstall endpoint (40hC4fh/80h8fh) these commands are used to stall or unstall an endpoint. the commands modify the content of the dcendpointstatus register (see ta b l e 9 2 ). a stalled control endpoint is automatically unstalled when it receives a setup token, regardless of the packet content. if the endpoint should stay in its stalled state, the microprocessor can re-stall it with the stall endpoint command. when a stalled endpoint is unstalled (either by the unstall endpoint command or by receiving a setup token), it is also re-initialized. this ?ushes the buffer: if it is an out buffer it waits for a data 0 pid, if it is an in buffer it writes a data 0 pid. code (hex): 40 to 4f stall (control out, control in, endpoint 1 to 14) code (hex): 80 to 8f unstall (control out, control in, endpoint 1 to 14) transaction none table 92: dcendpointstatus register: bit allocation bit 7 6 5 4 3 2 1 0 symbol epstal epfull1 epfull0 data_pid over write setupt cpubuf reserved reset 00000000 access rrrrrrrr table 93: dcendpointstatus register: bit description bit symbol description 7 epstal this bit indicates whether the endpoint is stalled or not (1 = stalled, 0 = not stalled). set to logic 1 by a stall endpoint command and cleared to logic 0 by an unstall endpoint command. the endpoint is automatically unstalled upon reception of a setup token. 6 epfull1 a logic 1 indicates that the secondary endpoint buffer is full. 5 epfull0 a logic 1 indicates that the primary endpoint buffer is full. 4 data_pid this bit indicates the data pid of the next packet (0 = data pid, 1 = data1 pid). 3 overwrite this bit is set by hardware, a logic 1 indicating that a new setup packet has overwritten the previous set-up information, before it was acknowledged or before the endpoint was stalled. if writing the set-up data has ?nished, this bit is cleared by a read action. firmware must check this bit before sending an acknowledge setup command or stalling the endpoint. upon reading a logic 1, the ?rmware must stop ongoing set-up actions and wait for a new setup packet. 2 setupt a logic 1 indicates that the buffer contains a setup packet. 1 cpubuf this bit indicates which buffer is currently selected for cpu access (0 = primary buffer, 1 = secondary buffer). 0 - reserved
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 102 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13.2.4 validate endpoint buffer (r/w: 6fh/61h) this command signals the presence of valid data for transmission to the usb host, by setting the buffer full ?ag of the selected in endpoint. this indicates that the data in the buffer is valid and can be sent to the host, when the next in token is received. for a double-buffered endpoint this command switches the current fifo for cpu access. remark: for special aspects of the control in endpoint see section 11.3.6 . code (hex): 61 to 6f validate endpoint buffer (control in, endpoint 1 to 14) transaction none 13.2.5 clear endpoint buffer (70h, 72hC7fh) this command unlocks and clears the buffer of the selected out endpoint, allowing the reception of new packets. reception of a complete packet causes the buffer full ?ag of an out endpoint to be set. any subsequent packets are refused by returning a nak condition, until the buffer is unlocked using this command. for a double-buffered endpoint this command switches the current fifo for cpu access. remark: for special aspects of the control out endpoint see section 11.3.6 . code (hex): 70, 72 to 7f clear endpoint buffer (control out, endpoint 1 to 14) transaction none 13.2.6 dcendpointstatusimage register(d0hCdfh) this command is used to check the status of the selected endpoint fifo without clearing any status or interrupt bits. the command accesses the dcendpointstatusimage register, which contains a copy of the dcendpointstatus register. the bit allocation of the dcendpointstatusimage register is shown in ta b l e 9 4 . code (hex): d0 to df check status (control out, control in, endpoint 1 to 14) transaction write/read 1 word table 94: dcendpointstatusimage register: bit allocation bit 7 6 5 4 3 2 1 0 symbol epstal epfull1 epfull0 data_pid over write setupt cpubuf reserved reset 00000000 access rrrrrrrr table 95: dcendpointstatusimage register: bit description bit symbol description 7 epstal this bit indicates whether the endpoint is stalled or not (1 = stalled, 0 = not stalled). 6 epfull1 a logic 1 indicates that the secondary endpoint buffer is full. 5 epfull0 a logic 1 indicates that the primary endpoint buffer is full. 4 data_pid this bit indicates the data pid of the next packet (0 = data pid, 1 = data1 pid).
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 103 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13.2.7 acknowledge setup (f4h) this command acknowledges to the host that a setup packet was received. the arrival of a setup packet disables the validate buffer and clear buffer commands for the control in and out endpoints. the microprocessor needs to re-enable these commands by sending an acknowledge setup command, see section 11.3.6 . code (hex): f4 acknowledge set-up transaction none 13.3 general commands 13.3.1 read endpoint error code (r: a0hCafh) this command returns the status of the last transaction of the selected endpoint, as stored in the dcerrorcode register. each new transaction overwrites the previous status information. the bit allocation of the dcerrorcode register is shown in ta b l e 9 6 . code (hex): a0 to af read error code (control out, control in, endpoint 1 to 14) transaction read 1 word 3 overwrite this bit is set by hardware, a logic 1 indicating that a new setup packet has overwritten the previous set-up information, before it was acknowledged or before the endpoint was stalled. if writing the set-up data has ?nished, this bit is cleared by a read action. firmware must check this bit before sending an acknowledge setup command or stalling the endpoint. upon reading a logic 1 the ?rmware must stop ongoing set-up actions and wait for a new setup packet. 2 setupt a logic 1 indicates that the buffer contains a setup packet. 1 cpubuf this bit indicates which buffer is currently selected for cpu access (0 = primary buffer, 1 = secondary buffer). 0 - reserved table 95: dcendpointstatusimage register: bit description continued bit symbol description table 96: dcerrorcode register: bit allocation bit 7 6 5 4 3 2 1 0 symbol unread data01 reserved error[3:0] rtok reset 00000000 access rrrrrrrr table 97: dcerrorcode register: bit description bit symbol description 7 unread a logic 1 indicates that a new event occurred before the previous status was read. 6 data01 this bit indicates the pid type of the last successfully received or transmitted packet (0 = data0 pid, 1 = data1 pid).
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 104 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13.3.2 unlock device (b0h) this command unlocks the isp1161a1s dc from write-protection mode after a resume. in suspend state all registers and fifos are write-protected to prevent data corruption by external devices during a resume. also, the register access for reading is possible only after the unlock device command is executed. after waking up from suspend state, the ?rmware must unlock the registers and fifos via this command, by writing the unlock code (aa37h) into the lock register. the bit allocation of the lock register is given in ta b l e 9 9 . code (hex): b0 unlock the device transaction write 1 word (unlock code) 5 - reserved 4 to 1 error[3:0] error code. for error description, see ta b l e 9 8 . 0 rtok a logic 1 indicates that data was received or transmitted successfully. table 98: transaction error codes error code (binary) description 0000 no error 0001 pid encoding error; bits 7 to 4 are not the inverse of bits 3 to 0 0010 pid unknown; encoding is valid, but pid does not exist 0011 unexpected packet; packet is not of the expected type (token, data, or acknowledge), or is a token to a non-control endpoint 0100 token crc error 0101 data crc error 0110 time-out error 0111 babble error 1000 unexpected end-of-packet 1001 sent or received nak (not acknowledge) 1010 sent stall; a token was received, but the endpoint was stalled 1011 over?ow; the received packet was larger than the available buffer space 1100 sent empty packet (iso only) 1101 bit stuf?ng error 1110 sync error 1111 wrong (unexpected) toggle bit in data pid; data was ignored table 97: dcerrorcode register: bit description continued bit symbol description table 99: lock register: bit allocation bit 15 14 13 12 11 10 9 8 symbol unlockh[7:0] reset aah access w
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 105 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13.3.3 dcscratch register (r/w: b3h/b2h) this command accesses the 16-bit dcscratch register, which can be used by the ?rmware to save and restore information, e.g., the device status before powering down in suspend state. the register bit allocation is given in table 101 . code (hex): b2/b3 write/read scratch register transaction write/read 1 word 13.3.4 read frame number (r: b4h) this command returns the frame number of the last successfully received sof. it is followed by reading one word from the dcframenumber register, containing the frame number. the dcframenumber register is shown in table 103 . remark: after a bus reset, the value of the dcframenumber register is unde?ned. code (hex): b4 read frame number transaction read 1 word bit 7 6 5 4 3 2 1 0 symbol unlockl[7:0] reset 37h access w table 100: lock register: bit description bit symbol description 15 to 0 unlock[15:0] sending data aa37h unlocks the internal registers and fifos for writing, following a resume. table 101: dcscratch register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved sfirh[4:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol sfirl[7:0] reset 00h access r/w table 102: dcscratch register: bit description bit symbol description 15 to 13 - reserved; must be logic 0 12 to 0 sfir[12:0] scratch information register
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 106 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] reset value unde?ned after a bus reset. 13.3.5 read chip id (r: b5h) this command reads the chip identi?cation code and hardware version number. the ?rmware must check this information to determine the supported functions and features. this command accesses the dcchipid register, which is shown in table 106 . code (hex): b5 read chip id transaction read 1 word table 103: dcframenumber register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved sofrh[2:0] reset [1] 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol sofrl[7:0] reset [1] 00000000 access rrrrrrrr table 104: dcframenumber register: bits description bit symbol description 15 to 11 - reserved 10 to 8 sofrh[2:0] sof frame number (upper byte) 7 to 0 sofrl[7:0] sof frame number (lower byte) table 105: example of dcframenumber register access a0 phase bus lines word # description 1 command d[7:0] - command code (b4h) d[15:8] - ignored 0 data d[15:0] 0 frame number table 106: dcchipid register: bit allocation bit 15 14 13 12 11 10 9 8 symbol chipidh[7:0] reset 61h access r bit 7 6 5 4 3 2 1 0 symbol chipidl[7:0] reset 23h access r
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 107 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13.3.6 read interrupt register (r: c0h) this command indicates the sources of interrupts as stored in the 4-byte dcinterrupt register. each individual endpoint has its own interrupt bit. the bit allocation of the dcinterrupt register is shown in table 108 . bit bustatus is used to verify the current bus status in the interrupt service routine. interrupts are enabled via the dcinterruptenable register, see section 13.1.5 . remark: while reading the dcinterrupt register, read both 2 bytes. code (hex): c0 read interrupt register transaction read 2 words remark: for details on interrupt control, see section 8.6.3 . table 107: dcchipid register: bit description bit symbol description 15 to 8 chipidh[7:0] chip id code (61h) 7 to 0 chipidl[7:0] silicon version (23h, with 23 representing the bcd encoded version number) table 108: dcinterrupt register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset 00h access r bit 23 22 21 20 19 18 17 16 symbol ep14 ep13 ep12 ep11 ep10 ep9 ep8 ep7 reset 00000000 access rrrrrrrr bit 15 14 13 12 11 10 9 8 symbol ep6 ep5 ep4 ep3 ep2 ep1 ep0in ep0out reset 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol bustatus sp_eot psof sof eot suspnd resume reset reset 00000000 access rrrrrrrr table 109: dcinterrupt register: bit description bit symbol description 31 to 24 - reserved 23 to 10 ep14 to ep1 a logic 1 indicates the interrupt source(s): endpoint 14 to 1. 9 ep0in a logic 1 indicates the interrupt source: control in endpoint. 8 ep0out a logic 1 indicates the interrupt source: control out endpoint. 7 bustatus monitors the current usb bus status (0 = awake, 1 = suspend). 6 sp_eot a logic 1 indicates that an eot interrupt has occurred for a short packet.
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 108 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 5 psof a logic 1 indicates that an interrupt is issued every 1 ms because of the pseudo sof; after 3 missed sofs suspend state is entered. 4 sof a logic 1 indicates that a sof condition was detected. 3 eot a logic 1 indicates that an internal eot condition was generated by the dma counter reaching zero. 2 suspnd a logic 1 indicates that an awake to suspend change of state was detected on the usb bus. 1 resume a logic 1 indicates that a resume state was detected. 0 reset a logic 1 indicates that a bus reset condition was detected. table 109: dcinterrupt register: bit description continued bit symbol description
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 109 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 14. power supply the isp1161a1 can operate at either 5 v or 3.3 v. when using 5 v as the isp1161a1s power supply input, only v cc (pin 56) can be connected to the 5 v power supply. an application with a 5 v power supply input is shown in figure 43 . the isp1161a1 has an internal dc/dc regulator to provide 3.3 v for its internal core. this internal 3.3 v can also be obtained from v reg(3.3) (pin 58) to supply the 1.5 k w pull-up resistor of the dc side upstream port signal d_dp. the signal d_dp is connected to the standard usb upstream port connectors pin d+. when using 3.3 v as the power supply input, the internal dc/dc regulator will be bypassed. all four power supply pins (v cc ,v reg(3.3) ,v hold1 and v hold2 ) can be used as power supply input. it is recommended that you connect all four power supply pins to the 3.3 v power supply, as shown in figure 44 . if, however, you have board space (routing area) constraints, you must connect at least v cc and v reg(3.3) to the 3.3 v power supply. for both 3.3 v and 5 v operation, all four power supply pins should be connected to a decoupling capacitor. 15. crystal oscillator and lazyclock the isp1161a1 has a crystal oscillator designed for a 6 mhz parallel-resonant crystal (fundamental). a typical circuit is shown in figure 45 . alternatively, an external clock signal of 6 mhz can be applied to input xtal1, while leaving output xtal2 open. see figure 46 . fig 43. using a 5 v supply. fig 44. using a 3.3 v supply. 004aaa188 1.5 k w d_dp gnd v cc v reg(3.3) v hold1 v hold2 to usb upstream port connector + 5 v isp1161a1 004aaa189 1.5 k w d_dp gnd v cc v reg(3.3) v hold1 v hold2 to usb upstream port connector + 3.3 v isp1161a1
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 110 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. the 6 mhz oscillator frequency is multiplied to 48 mhz by an internal pll. this frequency is used to generate a programmable clock output signal at pin clkout, ranging from 3 mhz to 48 mhz. in suspend state the normal clkout signal is not available, because the crystal oscillator and the pll are switched off to save power. instead, the clkout signal can be switched to the lazyclock frequency of 100 khz 50 %. the oscillator operation and the clkout frequency are controlled via the dchardwarecon?guration register, as shown in figure 47 . fig 45. oscillator circuit with external crystal. fig 46. oscillator circuit using external oscillator. 18 pf 6 mhz 18 pf 004aaa190 clkout xtal2 xtal1 isp1161a1 osc out n.c. 6 mhz 004aaa191 clkout xtal2 xtal1 isp1161a1 v cc
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 111 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. the following bits are involved: ? clkrun switches the oscillator on and off ? clkdiv[3:0] is the division factor determining the normal clkout frequency ? nolazy controls the lazyclock signal output during suspend state. for details about the dcs interrupt logic, see section 8.6.3 . when the isp1161a1s dc enters the suspend state (by setting and clearing bit gosusp in the dcmode register), outputs d_suspend and clkout change state after approximately 2 ms delay. when nolazy = 0 the clock signal on output clkout does not stop, but changes to the 100 khz 50 % lazyclock frequency. when resuming from suspend state by a positive pulse on input d_wakeup, output suspend is cleared and the clock signal on clkout restarted after a 0.5 ms delay. the timing of the clkout signal at suspend and resume is given in figure 48 . fig 47. oscillator and lazyclock logic. mgs775 clkrun hardware configuration register clkdiv [ 3:0 ] nolazy ? (n + 1) 1 0 n pll 8 xtal osc lazyclock enable enable 4 nolazy clkout enable 6 mhz 48 mhz suspend . . . . . . 100 (50 %) khz if enabled, the 100 50 % khz lazyclock frequency will be output on pin clkout during suspend state. fig 48. clkout signal timing at suspend and resume for dc. 004aaa038 d_wakeup gosusp 1.8 to 2.2 ms 0.5 ms pll circuit stable 3 to 4 ms d_suspend clkout
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 112 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 16. power-on reset (por) when v cc is directly connected to the reset pin, the internal pulse width (t porp ) will be typically (600 ns to 1000 ns) + x, when v cc is 3.3 v. x depends on how fast v cc is rising with respect to v trip (2.03 v). the time x is decided by the external power supply circuit. to give a better view of the functionality, figure 49 shows a possible curve of v cc(por) with dips at t2Ct3 and t4Ct5. if the dip at t4Ct5 is too short (that is, < 11 m s), the internal por pulse will not react and will remain low. the internal por starts with a 1 at t0. at t1, the detector will see the passing of the trip level and a delay element will add another t porp before it drops to 0. the internal por pulse will be generated whenever v cc(por) drops below v trip for more than 11 m s. even if v cc is 5.0 v, v trip still remains at 2.03 v. this is because the 5 v tolerant pads and on-chip voltage regulator ensure that 3.3 v is going to the internal por circuitry by clipping the voltage above 3.3 v. the reset pin can be either connected to v cc (using the internal por circuit) or externally controlled (by the micro, asic, and so on). figure 50 shows the availability of the clock with respect to the external por. (1) porp = power-on reset pulse. fig 49. internal por timing. stable external clock is available at a. fig 50. clock with respect to the external por. 004aaa389 v bat(por) t0 t1 t2 t3 t4 t5 v trip t porp porp (1) t porp por external clock a 004aaa365
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 113 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 17. limiting values [1] equivalent to discharging a 100 pf capacitor via a 1.5 k w resistor (human body model). 18. recommended operating conditions [1] 5 v tolerant. table 110: absolute maximum ratings in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v cc(5v) supply voltage on pin v cc - 0.5 + 6.0 v v cc(3.3v) supply voltage on pin v reg(3.3) - 0.5 + 4.6 v v i input voltage - 0.5 + 6.0 v i lu latch-up current v i < 0 or v i >v cc - 100 ma v esd electrostatic discharge voltage i li <1 m a [1] - 2000 + 2000 v t stg storage temperature - 60 + 150 c table 111: recommended operating conditions symbol parameter conditions min typ max unit v cc supply voltage with internal regulator 4.0 5.0 5.5 v internal regulator bypass 3.0 3.3 3.6 v v i input voltage [1] 0v cc 5.5 v v i(ai/o) input voltage on analog i/o pins (d + /d - ) 0 - 3.6 v v o(od) open-drain output pull-up voltage 0 - v cc v t amb ambient temperature - 40 - + 85 c
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 114 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 19. static characteristics [1] for typical values t amb =25 c. [2] in suspend mode, the minimum voltage is 2.7 v. table 112: static characteristics; supply pins v cc = 3.0 v to 3.6 v or 4.0 v to 5.5 v; v gnd =0v; t amb = - 40 cto + 85 c; unless otherwise speci?ed. symbol parameter conditions min typ [1] max unit v cc =5v v reg(3.3) internal regulator output typical at t amb =25 c [2] 3.0 3.3 3.6 v i cc operating supply current typical at t amb =25 c - 47 - ma i cc(susp ) suspend supply current typical at t amb =25 c - 40 500 m a i cc(hc ) operating supply current for hc dc is suspended; typical at t amb =25 c -22- ma i cc(dc ) operating supply current for dc hc is suspended; typical at t amb =25 c -18- ma v cc = 3.3 v i cc operating supply current typical at t amb =25 c - 50 - ma i cc(susp ) suspend supply current typical at t amb =25 c - 150 500 m a i cc(hc ) operating supply current for hc dc is suspended; typical at t amb =25 c -22- ma i cc(dc ) operating supply current for dc hc is suspended; typical at t amb =25 c -18- ma table 113: static characteristics: digital pins v cc = 3.0 v to 3.6 v or 4.0 v to 5.5 v; v gnd =0v; t amb = - 40 cto + 85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit d v trip overcurrent detection trip voltage -75-mv input levels v il low-level input voltage - - 0.8 v v ih high-level input voltage 2.0 - - v schmitt trigger inputs v th(lh) positive-going threshold voltage 1.4 - 1.9 v v th(hl) negative-going threshold voltage 0.9 - 1.5 v v hys hysteresis voltage 0.4 - 0.7 v output levels v ol low-level output voltage i ol = 4 ma - - 0.4 v i ol =20 m a - - 0.1 v v oh high-level output voltage i oh =4ma [1] 2.4 - - v i oh =20 m av reg(3.3) - 0.1 - - v
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 115 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] not applicable for open-drain outputs. [2] this maximum and minimum values are applicable to transistor input only. the value will be different if internal pull-up or pull-down resistors are used. [1] d + is the usb positive data pin; d - is the usb negative data pin. [2] includes external resistors of 18 w 1 % on both h_d + and h_d - . [3] in suspend mode, the minimum voltage is 2.7 v. leakage current i li input leakage current [2] - 5- + 5 m a c in pin capacitance pin to gnd - - 5 pf open-drain outputs i oz off-state output current - 5- + 5 m a table 113: static characteristics: digital pins continued v cc = 3.0 v to 3.6 v or 4.0 v to 5.5 v; v gnd =0v; t amb = - 40 cto + 85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit table 114: static characteristics: analog i/o pins (d + , d - ) v cc = 3.0 v to 3.6 v or 4.0 v to 5.5 v; v gnd =0v; t amb = - 40 cto + 85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit input levels v di differential input sensitivity | v i(d + ) - v i(d - ) | [1] 0.2 - - v v cm differential common mode voltage includes v di range 0.8 - 2.5 v v il low-level input voltage - - 0.8 v v ih high-level input voltage 2.0 - - v output levels v ol low-level output voltage r l = 1.5 k w to 3.6 v - - 0.3 v v oh high-level output voltage r l =15k w to gnd 2.8 - 3.6 v leakage current i lz off-state leakage current - - 10 m a capacitance c in transceiver capacitance pin to gnd - - 10 pf resistance r pd pull-down resistance on hcs pins dp/dm enable internal resistors 10 - 20 k w r pu pull-up resistance on pin d_dp softconnect = on 1 - 2 k w z drv driver output impedance steady-state drive [2] 29 - 44 w z inp input impedance 10 - - m w termination v term termination voltage for upstream port pull-up (r pu ) [3] 3.0 - 3.6 v
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 116 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 20. dynamic characteristics [1] dependent on the crystal oscillator start-up time. [1] test circuit; see figure 66 . [2] excluding the ?rst transition from idle state. [3] characterized only, not tested. limits guaranteed by design. table 115: dynamic characteristics v cc = 3.0 v to 3.6 v or 4.0 v to 5.5 v; v gnd =0v; t amb = - 40 cto + 85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit reset t w( reset) pulse width on input reset crystal oscillator running 160 - - m s crystal oscillator stopped [1] ---ms crystal oscillator f xtal crystal frequency - 6 - mhz r s series resistance - - 100 w c load load capacitance - 18 - pf external clock input t j external clock jitter - - 500 ps t duty clock duty cycle 45 50 55 % t cr , t cf rise time and fall time - - 3 ns table 116: dynamic characteristics: analog i/o pins (d + , d - ) [1] v cc = 3.0 v to 3.6 v or 4.0 v to 5.5 v; v gnd =0v;t amb = - 40 cto + 85 c; c l = 50 pf; r pu = 1.5 k w 5 % on d + to v term ; unless otherwise speci?ed. symbol parameter conditions min typ max unit driver characteristics t fr rise time c l =50pf; 10%to90% of | v oh - v ol | 4 - 20 ns t ff fall time c l =50pf; 90%to10% of | v oh - v ol | 4 - 20 ns frfm differential rise/fall time matching (t fr /t ff ) [2] 90 - 111.11 % v crs output signal crossover voltage [2][3] 1.3 - 2.0 v
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 117 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 20.1 programmed i/o timing ? if you are accessing only the hc, then the hc programmed i/o timing applies. ? if you are accessing only the dc, then the dc programmed i/o timing applies. ? if you are accessing both the hc and the dc, then the dc programmed i/o timing applies. 20.1.1 hc programmed i/o timing table 117: dynamic characteristics: hc programmed interface timing symbol parameter conditions min typ max unit t as address set-up time before wr high 5--ns t ah address hold time after wr high 8 - - ns read timing t shsl ?rst rd/wr after a0 high 300 - - ns t slrl cs low to rd low 0 - - ns t rhsh rd high to cs high 0 - - ns t rlrh rd low pulse width 33 - - ns t rhrl rd high to next rd low 110 - - ns t rc rd cycle time 143 - - ns t rhdz rd data hold time 3 - 22 ns t rldv rd low to data valid - - 32 ns write timing t wl wr low pulse width 26 - - ns t whwl wr high to next wr low 110 - - ns t wc wr cycle time 136 - - ns t slwl cs low to wr low 0 - - ns t whsh wr high to cs high 0 - - ns t wdsu wr data set-up time 5 - - ns t wdh wr data hold time 8 - - ns
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 118 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 20.1.2 dc programmed i/o timing fig 51. hc programmed interface timing mgt969 a0 d [ 15:0 ] d [ 15:0 ] wr rd cs data valid data valid data valid data valid data valid data valid data valid data valid data valid t shsl t rlrh t rhrl t rldv t wl t whwl t wdh t wdsu t rc t wc t rhdz t slrl t rhsh t slwl t whsh t ah t as table 118: dynamic characteristics: dc programmed interface timing symbol parameter conditions min typ max unit read timing (see figure 52 ) t rhax address hold time after rd high 0 - - ns t avrl address set-up time before rd low 0 - - ns t shdz data outputs high-impedance time after cs high - - 3 ns t rhsh chip deselect time after rd high 0 - - ns t rlrh rd pulse width 25 - - ns t rldv data valid time after rd low - - 22 ns t shrl cs high until next isp1161a1 rd 120 - - ns t shrl +t rlrh read cycle time 180 - - ns write timing (see figure 53 ) t whax address hold time after wr high 1 - - ns t avwl address set-up time before wr low 0 - - ns t shwl cs high until next isp1161a1 wr 120 - - ns t shwl +t wlwh write cycle time 180 - - ns t wlwh wr pulse width 22 - - ns t whsh chip deselect time after wr high 0 - - ns t dvwh data set-up time before wr high 5 - - ns t whdz data hold time after wr high 3 - - ns
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 119 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 20.2 dma timing 20.2.1 hc single-cycle dma timing (1) for t shrl both cs and rd must be de-asserted. (2) programmable polarity: shown as active low. fig 52. dc programmed interface read timing (i/o and 8237 compatible dma). 004aaa105 a0 t rhax t avrl t rlrh t rldv t shdz t shrl (1) d[15:0] rd cs/dack2 (2) t rhsh (1) for t shwl both cs and wr must be de-asserted. (2) programmable polarity: shown as active low. fig 53. dc programmed interface write timing (i/o and 8237 compatible dma). 004aaa106 cs/dack2 (2) a0 d[15:0] wr t whax t avwl t whdz t dvwh t wlwh t whsh t shwl (1) table 119: dynamic characteristics: hc single-cycle dma timing symbol parameter conditions min typ max unit read/write timing t rlrh rd pulse width 33 - - ns t rldv read process data set-up time 26 - - ns
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 120 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] t rhal +t ds +t alrl . 20.2.2 hc burst mode dma timing t rhdz read process data hold time 0 - 20 ns t wsu write process data set-up time 5 - - ns t whd write process data hold time 0 - - ns t ahrh d a ck1 high to dreq1 high 72 - - ns t alrl d a ck1 low to dreq1 low - - 21 ns t dc dreq1 cycle [1] ---ns t shah rd/wr high to d a ck1 high 0 - - ns t rhal dreq1 high to d a ck1 low 0 - - ns t ds dreq1 pulse spacing 146 - - ns table 119: dynamic characteristics: hc single-cycle dma timing continued symbol parameter conditions min typ max unit fig 54. hc single-cycle dma timing. 004aaa107 dreq1 dack1 d [ 15:0 ] (read) d [ 15:0 ] (write) rd or wr t ds t ahrh t dc data valid data valid t alrl t rhal t whd t wsu t rldv t rhdz t shah table 120: dynamic characteristics: hc burst mode dma timing symbol parameter conditions min typ max unit read/write timing (for 4-cycle and 8-cycle burst mode) t rlrh wr/rd low pulse width 42 - - ns t rhrl wr/rd high to next wr/rd low 60 - - ns t rc wr/rd cycle 102 - - ns t slrl rd/wr low to dreq1 low 22 - 64 ns t shah rd/wr high to d a ck1 high 0 - - ns t slal dreq1 high to d a ck1 low 0 - ns
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 121 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] t slal + (4 or 8)t rc +t ds . t dc dreq1 cycle [1] ---ns t ds(read) dreq1 pulse spacing (read) 4-cycle burst mode 105 - - ns 8-cycle burst mode 150 - - ns t ds(write) dreq1 pulse spacing (write) 4-cycle burst mode 72 - - ns 8-cycle burst mode 167 - - ns t rlis rd/wr low to eot low 0 - - ns table 120: dynamic characteristics: hc burst mode dma timing continued symbol parameter conditions min typ max unit fig 55. hc burst mode dma timing. 004aaa108 t rhrl t ds t rhsh dreq1 dack1 rd or wr t slrl t shah t rlrh t rc t rhal
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 122 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 20.2.3 external eot timing for hc single-cycle dma 20.2.4 external eot timing for hc burst mode dma 20.2.5 dc single-cycle dma timing (8237 mode) fig 56. external eot timing for hc single-cycle dma. 004aaa109 dreq1 dack1 eot t rlis > 0 ns rd or wr fig 57. external eot timing for hc burst mode dma. 004aaa110 dreq1 dack1 eot t rlis > 0 ns rd or wr table 121: dynamic characteristics: dc single-cycle dma timing (8237 mode) symbol parameter conditions min typ max unit t asrp dreq2 off after d a ck2 on - - 40 ns t cy(dreq2) cycle time signal dreq2 180 - - ns (1) programmable polarity: shown as active low. fig 58. dc single-cycle dma timing (8237 mode). 004aaa111 dreq2 dack2 (1) t asrp t rc
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 123 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 20.2.6 dc single-cycle dma read timing in dack-only mode 20.2.7 dc single-cycle dma write timing in dack-only mode table 122: dynamic characteristics: dc single-cycle dma read timing in dack-only mode symbol parameter conditions min typ max unit t asrp dreq off after d a ck on - - 40 ns t asap d a ck pulse width 25 - - ns t asap +t aprs dreq on after d a ck off 180 - - ns t asdv data valid after d a ck on - - 22 ns t apdz data hold after d a ck off - - 3 ns (1) programmable polarity: shown as active low. fig 59. dc single-cycle dma read timing in dack-only mode. 004aaa112 dack2 (1) dreq2 t asrp t aprs t asdv t apdz data t asap table 123: dynamic characteristics: dc single-cycle dma write timing in dack-only mode symbol parameter conditions min typ max unit t asrp dreq2 off after d a ck2 on - - 40 ns t asap +t aprs dreq2 on after d a ck2 off 180 - - ns t dvap data set-up before d a ck2 off 5 - - ns t apdz data hold after d a ck2 off 3 - - ns (1) programmable polarity: shown as active low. fig 60. dc single-cycle dma write timing in dack-only mode. 004aaa113 dack2 (1) dreq2 t asrp t aprs t asdv t apdz data t asap
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 124 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 20.2.8 eot timing in dc single-cycle dma 20.2.9 dc burst mode dma timing table 124: dynamic characteristics: eot timing in dc single-cycle dma symbol parameter conditions min typ max unit t rsih input rd/ wr high after dreq on 22--ns t ihap d a ck off after input rd/ wr high 0--ns t eot eot pulse width eot on; d a ck on; rd/ wr low 22--ns t rlis input eot on after rd low - - 89 ns t wlis input eot on after wr low - 89 ns (1) t asrp starts from d a ck or rd/ wr going low, whichever occurs later. (2) the rd/ wr signals are not used in dack-only dma mode. (3) the eot condition is considered valid if d a ck, rd/ wr and eo t are all active (= low). (4) programmable polarity: shown as active low. fig 61. eot timing in dc single-cycle dma. 004aaa114 dreq2 t rsih t ihap t asrp (1) t eot (3) t rlis t wlis eot (4) dack2 (4) rd/wr (2) table 125: dynamic characteristics: dc burst mode dma timing symbol parameter conditions min typ max unit t rsih input rd/ wr high after dreq on 22 - - ns t ilrp dreq off after input rd/ wr low - - 60 ns t ihap d a ck off after input rd/ wr high 0 - - ns t ihil dma burst repeat interval (input rd/ wr high to low) 180 - - ns
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 125 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 20.2.10 eot timing in dc burst mode dma (1) programmable polarity: shown as active low. fig 62. dc burst mode dma timing. 004aaa115 dack2 (1) dreq2 t rsih t ilrp t ihil t ihap rd or wr table 126: dynamic characteristics: eot timing in dc burst mode dma symbol parameter conditions min typ max unit t eot eot pulse width eot on; d a ck on; rd/ wr low 22--ns t isrp dreq off after input eot on - - 40 ns t rlis input eot on after rd low - - 89 ns t wlis input eot on after wr low - - 89 ns (1) the eot condition is considered valid if d a ck2, rd/ wr and eo t are all active (= low). (2) programmable polarity: shown as active low. fig 63. eot timing in dc burst mode dma. 004aaa116 dack2 (2) dreq2 t isrp t eot (1) rd/wr eot (2) t rlis t wlis
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 126 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 21. application information 21.1 typical interface circuit (1) for mosfet, r dson = 150 m w . (2) 470 w assuming that v cc is 5.0 v. fig 64. typical interface circuit to hitachi sh-3 (sh7709) risc processor. 004aaa192 470 w (2) led fb4 fb6 fb3 fb2 fb1 22 w (2 ) 18 pf 18 pf + 5 v + 3.3 v + 3.3 v + 5 v v dd + 5 v + 5 v vbus_dn2 vbus_dn1 + 3.3 v + 5 v sh7709 a1 a0 mosfet (2 ) (1) usb downstream port #1 usb downstream port #2 d [ 15:0 ] d [ 15:0 ] a2 a1 dreq0 dreq1 dack0 dack1 dreq1 dreq2 cs5 cs rd rd rd/wr wr dack1 dack2 eot ptc0 h_wakeup ptc1 h_suspend ptc2 d_wakeup ptc3 d_suspend gnd xtal2 extal2 32 khz 6 mhz xtal extal dgnd agnd irq2 int1 irq3 int2 rstout reset isp1161a1 clkout clkout h_oc1 h_oc2 h_psw2 h_psw1 v cc v reg(3.3) v hold1 v hold2 h_dm1 h_dp1 h_dm2 h_dp2 d_dm d_dp ndp_sel gl d_vbus clkout xtal2 xtal1 v reg v dd v dd + 3.3 v usb upstream port 22 w (2 ) 47 pf (2 ) vbus_up fb5 22 w (2 ) 7 1.5 k w v reg 47 pf (2 ) 47 pf (2 )
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 127 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 21.2 interfacing a isp1161a1 with a sh7709 risc processor this section shows a typical interface circuit between the isp1161a1 and a risc processor. the hitachi sh-3 series risc processor sh7709 is used as the example. the main isp1161a1 signals to be taken into consideration for connecting to a sh7709 risc processor are: ? a 16-bit data bus: d[15:0] for the isp1161a1. the isp1161a1 is little endian compatible. ? two address lines a1 and a0 are needed for a complete addressing of the isp1161a1 internal registers: C a1 = 0 and a0 = 0 will select the data port of the host controller C a1 = 0 and a0 = 1 will select the command port of the host controller C a1 = 1 and a0 = 0 will select the data port of the device controller C a1 = 1 and a0 = 1 will select the command port of the device controller ? the cs line is used for chip selection of the isp1161a1 in a certain address range of the risc system. this signal is active low. ? rd and wr are common read and write signals. these signals are active low. ? there are two dma channel standard control lines: C dreq1 and d a ck1 C dreq2 and d a ck2 (in each case one channel is used by the hc and the other channel is used by the dc). these signals have programmable active levels. ? two interrupt lines: int1 (used by the hc) and int2 (used by the device controller). both have programmable level/edge and polarity (active high or low). ? the internal 15 k w pull-down resistors are used for the hcs two usb downstream ports. ? the reset signal is active low. remark: sh7709s system clock input is for reference only. refer to sh7709s speci?cation for its actual use. the isp1161a1 can work under either 3.3 v or 5.0 v power supply; however, its internal core works at 3.3 v. when using 3.3 v as the power supply input, the internal dc/dc regulator will be bypassed. it is best to connect all four power supply pins (v cc ,v reg(3.3) ,v hold1 and v hold2 ) to the 3.3 v power supply (for more information, see section 14 ). all of the isp1161a1s i/o pins are 5 v tolerant. this feature allows the isp1161a1 the ?exibility to be used in an embedded system under either a 3.3 v or a 5 v power supply. a typical sh7709 interface circuit is shown in figure 64 . 21.3 typical software model this section shows a typical software requirement for an embedded system that incorporates the isp1161a1. the software model for a digital still camera (dsc) is used as the example for illustration (as shown in figure 65 ). two components of system software are required to make full use of the features in the isp1161a1: the
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 128 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. host stack and the device stack. the device stack provides api directly to the application task for device function; the host stack provides api for class driver and device driver, both of which provide api for application tasks for host function. fig 65. isp1161a1 software model for dsc application. printer pc flash card reader/ writer usb upstream usb downstream digital still camera risc rom ram isp1161a1 len control 004aaa193 mechanism control task image processing tasks file management os printer ui/control printing class driver host stack device stack usb host/device stack class driver application layer file transfer device drivers mass storage class driver isp1161a1 hal
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 129 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 22. test information the dynamic characteristics of the analog i/o ports (d + and d -) as listed in table 116 were determined using the circuit shown in figure 66 . load capacitance: c l = 50 pf (full-speed mode). speed: full-speed mode only: internal 1.5 k w pull-up resistor on d_dp. fig 66. load impedance for pins d_dp and d_dm. mgt967 15 k w 22 w test point c l 50 pf d.u.t.
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 130 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 23. package outline fig 67. lqfp64 (sot314-2) package outline. unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 0.5 12.15 11.85 1.45 1.05 7 0 o o 0.12 0.1 1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot314-2 ms-026 136e10 00-01-19 03-02-25 d (1) (1) (1) 10.1 9.9 h d 12.15 11.85 e z 1.45 1.05 d b p e q e a 1 a l p detail x l (a ) 3 b 16 c d h b p e h a 2 v m b d z d a z e e v m a x 1 64 49 48 33 32 17 y pin 1 index w m w m 0 2.5 5 mm scale lqfp64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm sot314-2
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 131 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 68. lqfp64 (sot414-1) package outline. unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 1.6 0.15 0.05 1.45 1.35 0.25 0.23 0.13 0.20 0.09 7.1 6.9 0.4 9.15 8.85 0.64 0.36 7 0 o o 0.08 0.08 1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot414-1 136e06 ms-026 00-01-19 03-02-20 d (1) (1) (1) 7.1 6.9 h d 9.15 8.85 e z 0.64 0.36 d b p e q e a 1 a l p detail x l (a ) 3 b 16 c d h b p e h a 2 v m b d z d a z e e v m a x 1 64 49 48 33 32 17 y pin 1 index w m w m 0 2.5 5 mm scale lqfp64: plastic low profile quad flat package; 64 leads; body 7 x 7 x 1.4 mm sot414-1
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 132 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. 24. soldering 24.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. in these situations re?ow soldering is recommended. 24.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: ? below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson..t and ssop..t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. ? below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 24.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 133 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 24.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 24.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . table 127: suitability of surface mount ic packages for wave and re?ow soldering methods package [1] soldering method wave re?ow [2] bga, htsson..t [3] , lbga, lfbga, sqfp, ssop..t [3] , tfbga, uson, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable [4] suitable plcc [5] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [5][6] suitable ssop, tssop, vso, vssop not recommended [7] suitable cwqccn..l [8] , pmfp [9] , wqccn..l [8] not suitable not suitable
philips semiconductors isp1161a1 usb single-chip host and device controller product data rev. 03 23 december 2004 134 of 136 9397 750 13961 ? koninklijke philips electronics n.v. 2004. all rights reserved. [3] these transparent plastic packages are extremely sensitive to re?ow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re?ow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re?ow oven. the package body peak temperature must be kept as low as possible. [4] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [6] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] wave soldering is suitable for ssop, tssop, vso and vsop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on ?ex foil. however, the image sensor package can be mounted by the client on a ?ex foil by using a hot bar soldering process. the appropriate soldering pro?le can be provided on request. [9] hot bar soldering or manual soldering is suitable for pmfp packages. 25. revision history table 128: revision history rev date cpcn description 03 20041223 200412020 product data (9397 750 13961) modi?cations: ? section 9.8.1 using an internal oc detection circuit : fourth paragraph, second sentence, changed source to drain and drain to source ? section 11.4 suspend and resume : updated the entire section ? removed section 20.1 timing symbols ? table 118 dynamic characteristics: dc programmed interface timing : changed the min value of t rhax from 3 ns to 0 ns and of t whax from 3 ns to 1 ns, and added t shrl and t shwl . 02 20030825 - product data (9397 750 11828) 01 20021220 - product data (9397 750 10241)
9397 750 13961 philips semiconductors isp1161a1 usb single-chip host and device controller ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 03 23 december 2004 135 of 136 contact information for additional information, please visit http://www.semiconductors.philips.com . for sales of?ce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com . fax: +31 40 27 24825 26. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 27. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 28. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 29. trademarks arm7 and arm9 are trademarks of arm ltd. goodlink is a trademark of koninklijke philips electronics n.v. hitachi is a registered trademark of hitachi ltd. mips-based is a trademark of mips technologies, inc. softconnect is a trademark of koninklijke philips electronics n.v. strongarm is a registered trademark of arm ltd. superh is a trademark of hitachi ltd. level data sheet status [1] product status [2][3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
? koninklijke philips electronics n.v. 2004. printed in the netherlands all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 23 december 2004 document order number: 9397 750 13961 contents philips semiconductors isp1161a1 usb single-chip host and device controller 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 ordering information . . . . . . . . . . . . . . . . . . . . . 4 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 7 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 functional description . . . . . . . . . . . . . . . . . . 11 7.1 pll clock multiplier. . . . . . . . . . . . . . . . . . . . . 11 7.2 bit clock recovery . . . . . . . . . . . . . . . . . . . . . . 11 7.3 analog transceivers . . . . . . . . . . . . . . . . . . . . 11 7.4 philips serial interface engine (sie). . . . . . . . 11 7.5 softconnect . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.6 goodlink . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8 microprocessor bus interface. . . . . . . . . . . . . 12 8.1 programmed i/o (pio) addressing mode . . . . 12 8.2 dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.3 control register access by pio mode . . . . . . . 13 8.4 fifo buffer ram access by pio mode . . . . . 16 8.5 fifo buffer ram access by dma mode. . . . . 17 8.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9 usb host controller (hc). . . . . . . . . . . . . . . . . 24 9.1 hcs four usb states . . . . . . . . . . . . . . . . . . . 24 9.2 generating usb traf?c . . . . . . . . . . . . . . . . . . 24 9.3 ptd data structure . . . . . . . . . . . . . . . . . . . . . 26 9.4 hc internal fifo buffer ram structure . . . . . 29 9.5 hc operational model . . . . . . . . . . . . . . . . . . . 35 9.6 microprocessor loading. . . . . . . . . . . . . . . . . . 38 9.7 internal pull-down resistors for downstream ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.8 oc detection and power switching control . . . 39 9.9 suspend and wake-up . . . . . . . . . . . . . . . . . . 41 10 hc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.1 hc control and status registers . . . . . . . . . . . 45 10.2 hc frame counter registers. . . . . . . . . . . . . . . 52 10.3 hc root hub registers . . . . . . . . . . . . . . . . . . 55 10.4 hc dma and interrupt control registers . . . . . 65 10.5 hc miscellaneous registers . . . . . . . . . . . . . . 70 10.6 hc buffer ram control registers . . . . . . . . . . . 72 11 usb device controller (dc) . . . . . . . . . . . . . . . 77 11.1 dc data transfer operation . . . . . . . . . . . . . . . 77 11.2 device dma transfer. . . . . . . . . . . . . . . . . . . . 78 11.3 endpoint descriptions . . . . . . . . . . . . . . . . . . . 79 11.4 suspend and resume . . . . . . . . . . . . . . . . . . . 82 12 dc dma transfer . . . . . . . . . . . . . . . . . . . . . . . 85 12.1 selecting an endpoint for dma transfer . . . . . 85 12.2 8237 compatible mode . . . . . . . . . . . . . . . . . . 86 12.3 dack-only mode . . . . . . . . . . . . . . . . . . . . . . 87 12.4 end-of-transfer conditions. . . . . . . . . . . . . . . 88 13 dc commands and registers . . . . . . . . . . . . . 90 13.1 initialization commands . . . . . . . . . . . . . . . . . 92 13.2 data ?ow commands . . . . . . . . . . . . . . . . . . . 99 13.3 general commands . . . . . . . . . . . . . . . . . . . 103 14 power supply . . . . . . . . . . . . . . . . . . . . . . . . . 109 15 crystal oscillator and lazyclock . . . . . . . . . 109 16 power-on reset (por) . . . . . . . . . . . . . . . . . . 112 17 limiting values . . . . . . . . . . . . . . . . . . . . . . . 113 18 recommended operating conditions . . . . . 113 19 static characteristics . . . . . . . . . . . . . . . . . . 114 20 dynamic characteristics . . . . . . . . . . . . . . . . 116 20.1 programmed i/o timing . . . . . . . . . . . . . . . . 117 20.2 dma timing. . . . . . . . . . . . . . . . . . . . . . . . . . 119 21 application information . . . . . . . . . . . . . . . . 126 21.1 typical interface circuit . . . . . . . . . . . . . . . . . 126 21.2 interfacing a isp1161a1 with a sh7709 risc processor. . . . . . . . . . . . . . . . . . . . . . 127 21.3 typical software model . . . . . . . . . . . . . . . . . 127 22 test information. . . . . . . . . . . . . . . . . . . . . . . 129 23 package outline . . . . . . . . . . . . . . . . . . . . . . . 130 24 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 24.1 introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 24.2 re?ow soldering. . . . . . . . . . . . . . . . . . . . . . 132 24.3 wave soldering. . . . . . . . . . . . . . . . . . . . . . . 132 24.4 manual soldering . . . . . . . . . . . . . . . . . . . . . 133 24.5 package related soldering information . . . . . 133 25 revision history . . . . . . . . . . . . . . . . . . . . . . 134 26 data sheet status. . . . . . . . . . . . . . . . . . . . . . 135 27 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 28 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 135 29 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 135

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